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| LatticeXP2TM Family Data Sheet DS1009 Version 01.6, August 2008 LatticeXP2 Family Data Sheet Introduction February 2008 Data Sheet DS1009 Features flexiFLASHTM Architecture * * * * * * Instant-on Infinitely reconfigurable Single chip FlashBAKTM technology Serial TAG memory Design security Flexible I/O Buffer * sysIOTM buffer supports: - LVCMOS 33/25/18/15/12; LVTTL - SSTL 33/25/18 class I, II - HSTL15 class I; HSTL18 class I, II - PCI - LVDS, Bus-LVDS, MLVDS, LVPECL, RSDS Live Update Technology * TransFRTM technology * Secure updates with 128 bit AES encryption * Dual-boot with external SPI Pre-engineered Source Synchronous Interfaces * DDR / DDR2 interfaces up to 200 MHz * 7:1 LVDS interfaces support display applications * XGMII sysDSPTM Block * Three to eight blocks for high performance Multiply and Accumulate * 12 to 32 18x18 multipliers * Each block supports one 36x36 multiplier or four 18x18 or eight 9x9 multipliers Density And Package Options * 5k to 40k LUT4s, 86 to 540 I/Os * csBGA, TQFP PQFP ftBGA and fpBGA packages , , * Density migration supported Flexible Device Configuration * SPI (master and slave) Boot Flash Interface * Dual Boot Image supported * Soft Error Detect (SED) macro embedded Embedded and Distributed Memory * Up to 885 Kbits sysMEMTM EBR * Up to 83 Kbits Distributed RAM System Level Support * IEEE 1149.1 and IEEE 1532 Compliant * On-chip oscillator for initialization & general use * Devices operate with 1.2V power supply sysCLOCKTM PLLs * Up to four analog PLLs per device * Clock multiply, divide and phase shifting Table 1-1. LatticeXP2 Family Selection Guide Device LUTs (K) Distributed RAM (KBits) EBR SRAM (KBits) EBR SRAM Blocks sysDSP Blocks 18 x 18 Multipliers VCC Voltage GPLL Max Available I/O Packages and I/O Combinations 132-Ball csBGA (8 x 8 mm) 144-Pin TQFP (20 x 20 mm) 208-Pin PQFP (28 x 28 mm) 256-Ball ftBGA (17 x17 mm) 484-Ball fpBGA (23 x 23 mm) 672-Ball fpBGA (27 x 27 mm) 86 100 146 172 86 100 146 201 XP2-5 5 10 166 9 3 12 1.2 2 172 XP2-8 8 18 221 12 4 16 1.2 2 201 XP2-17 17 35 276 15 5 20 1.2 4 358 XP2-30 29 56 387 21 7 28 1.2 4 472 XP2-40 40 83 885 48 8 32 1.2 4 540 146 201 358 201 363 472 363 540 (c) 2008 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. www.latticesemi.com 1-1 DS1009 Introduction_01.2 Lattice Semiconductor Introduction LatticeXP2 Family Data Sheet Introduction LatticeXP2 devices combine a Look-up Table (LUT) based FPGA fabric with non-volatile Flash cells in an architecture referred to as flexiFLASH. The flexiFLASH approach provides benefits including instant-on, infinite reconfigurability, on chip storage with FlashBAK embedded block memory and Serial TAG memory and design security. The parts also support Live Update technology with TransFR, 128-bit AES Encryption and Dual-boot technologies. The LatticeXP2 FPGA fabric was optimized for the new technology from the outset with high performance and low cost in mind. LatticeXP2 devices include LUT-based logic, distributed and embedded memory, Phase Locked Loops (PLLs), pre-engineered source synchronous I/O support and enhanced sysDSP blocks. The ispLEVER(R) design tool from Lattice allows large and complex designs to be efficiently implemented using the LatticeXP2 family of FPGA devices. Synthesis library support for LatticeXP2 is available for popular logic synthesis tools. The ispLEVER tool uses the synthesis tool output along with the constraints from its floor planning tools to place and route the design in the LatticeXP2 device. The ispLEVER tool extracts the timing from the routing and back-annotates it into the design for timing verification. Lattice provides many pre-designed Intellectual Property (IP) ispLeverCORETM modules for the LatticeXP2 family. By using these IPs as standardized blocks, designers are free to concentrate on the unique aspects of their design, increasing their productivity. 1-2 LatticeXP2 Family Data Sheet Architecture August 2008 Data Sheet DS1009 Architecture Overview Each LatticeXP2 device contains an array of logic blocks surrounded by Programmable I/O Cells (PIC). Interspersed between the rows of logic blocks are rows of sysMEMTM Embedded Block RAM (EBR) and a row of sysDSPTM Digital Signal Processing blocks as shown in Figure 2-1. On the left and right sides of the Programmable Functional Unit (PFU) array, there are Non-volatile Memory Blocks. In configuration mode the nonvolatile memory is programmed via the IEEE 1149.1 TAP port or the sysCONFIGTM peripheral port. On power up, the configuration data is transferred from the Non-volatile Memory Blocks to the configuration SRAM. With this technology, expensive external configuration memory is not required, and designs are secured from unauthorized read-back. This transfer of data from non-volatile memory to configuration SRAM via wide busses happens in microseconds, providing an "instant-on" capability that allows easy interfacing in many applications. LatticeXP2 devices can also transfer data from the sysMEM EBR blocks to the Non-volatile Memory Blocks at user request. There are two kinds of logic blocks, the PFU and the PFU without RAM (PFF). The PFU contains the building blocks for logic, arithmetic, RAM and ROM functions. The PFF block contains building blocks for logic, arithmetic and ROM functions. Both PFU and PFF blocks are optimized for flexibility allowing complex designs to be implemented quickly and efficiently. Logic Blocks are arranged in a two-dimensional array. Only one type of block is used per row. LatticeXP2 devices contain one or more rows of sysMEM EBR blocks. sysMEM EBRs are large dedicated 18Kbit memory blocks. Each sysMEM block can be configured in a variety of depths and widths of RAM or ROM. In addition, LatticeXP2 devices contain up to two rows of DSP Blocks. Each DSP block has multipliers and adder/accumulators, which are the building blocks for complex signal processing capabilities. Each PIC block encompasses two PIOs (PIO pairs) with their respective sysIO buffers. The sysIO buffers of the LatticeXP2 devices are arranged into eight banks, allowing the implementation of a wide variety of I/O standards. In addition, a separate I/O bank is provided for programming interfaces. PIO pairs on the left and right edges of the device can be configured as LVDS transmit/receive pairs. The PIC logic also includes pre-engineered support to aid in the implementation of high speed source synchronous standards such as 7:1 LVDS interfaces, found in many display applications, and memory interfaces including DDR and DDR2. Other blocks provided include PLLs and configuration functions. The LatticeXP2 architecture provides up to four General Purpose PLLs (GPLL) per device. The GPLL blocks are located in the corners of the device. The configuration block that supports features such as configuration bit-stream de-encryption, transparent updates and dual boot support is located between banks two and three. Every device in the LatticeXP2 family supports a sysCONFIG port, muxed with bank seven I/Os, which supports serial device configuration. A JTAG port is provided between banks two and three. This family also provides an on-chip oscillator and Soft Error Detect (SED) capability. LatticeXP2 devices use 1.2V as their core voltage. (c) 2008 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. www.latticesemi.com 2-1 DS1009 Architecture_01.4 Lattice Semiconductor Figure 2-1. Simplified Block Diagram, LatticeXP2-17 Device (Top Level) Architecture LatticeXP2 Family Data Sheet sysIO Buffers, Pre-Engineered Source Synchronous Support On-chip Oscillator Programmable Function Units (PFUs) SPI Port sysMEM Block RAM JTAG Port DSP Blocks Flash sysCLOCK PLLs Flexible Routing PFU Blocks The core of the LatticeXP2 device is made up of logic blocks in two forms, PFUs and PFFs. PFUs can be programmed to perform logic, arithmetic, distributed RAM and distributed ROM functions. PFF blocks can be programmed to perform logic, arithmetic and ROM functions. Except where necessary, the remainder of this data sheet will use the term PFU to refer to both PFU and PFF blocks. Each PFU block consists of four interconnected slices, numbered Slice 0 through Slice 3, as shown in Figure 2-2. All the interconnections to and from PFU blocks are from routing. There are 50 inputs and 23 outputs associated with each PFU block. 2-2 Lattice Semiconductor Figure 2-2. PFU Diagram From Routing Architecture LatticeXP2 Family Data Sheet LUT4 & CARRY LUT4 & CARRY LUT4 & CARRY LUT4 & CARRY LUT4 & CARRY LUT4 & CARRY LUT4 LUT4 Slice 0 Slice 1 Slice 2 Slice 3 D D D D D D FF FF FF FF FF FF To Routing Slice Slice 0 through Slice 2 contain two 4-input combinatorial Look-Up Tables (LUT4), which feed two registers. Slice 3 contains two LUT4s and no registers. For PFUs, Slice 0 and Slice 2 can also be configured as distributed memory, a capability not available in PFF blocks. Table 2-1 shows the capability of the slices in both PFF and PFU blocks along with the operation modes they enable. In addition, each PFU contains logic that allows the LUTs to be combined to perform functions such as LUT5, LUT6, LUT7 and LUT8. There is control logic to perform set/reset functions (programmable as synchronous/asynchronous), clock select, chip-select and wider RAM/ROM functions. Figure 2-3 shows an overview of the internal logic of the slice. The registers in the slice can be configured as positive/negative edge triggered or level sensitive clocks. Table 2-1. Resources and Modes Available per Slice PFU BLock Slice Slice 0 Slice 1 Slice 2 Slice 3 Resources 2 LUT4s and 2 Registers 2 LUT4s Modes Logic, Ripple, ROM Logic, ROM Resources 2 LUT4s and 2 Registers 2 LUT4s PFF Block Modes Logic, Ripple, ROM Logic, Ripple, ROM Logic, Ripple, ROM Logic, ROM 2 LUT4s and 2 Registers Logic, Ripple, RAM, ROM 2 LUT4s and 2 Registers 2 LUT4s and 2 Registers Logic, Ripple, RAM, ROM 2 LUT4s and 2 Registers Slice 0 through Slice 2 have 14 input signals: 13 signals from routing and one from the carry-chain (from the adjacent slice or PFU). There are seven outputs: six to routing and one to carry-chain (to the adjacent PFU). Slice 3 has 13 input signals from routing and four signals to routing. Table 2-2 lists the signals associated with Slice 0 to Slice 2. 2-3 Lattice Semiconductor Figure 2-3. Slice Diagram FCO from Slice/PFU, FCI into Different Slice/PFU Architecture LatticeXP2 Family Data Sheet SLICE FXB FXA A1 B1 C1 D1 CO LUT4 & CARRY* CI OFX1 F/SUM D FF* To Routing LUT5 Mux F1 Q1 M1 M0 From Routing OFX0 A0 B0 C0 D0 CO LUT4 & CARRY* CI F0 F/SUM D FF* Q0 CE CLK LSR * Not in Slice 3 FCI into Slice/PFU, FCO from Different Slice/PFU For Slices 0 and 2, memory control signals are generated from Slice 1 as follows: WCK is CLK WRE is from LSR DI[3:2] for Slice 2 and DI[1:0] for Slice 0 data WAD [A:D] is a 4bit address from slice 1 LUT input Table 2-2. Slice Signal Descriptions Function Input Input Input Input Input Input Input Input Input Input Output Output Output Output Output Type Data signal Data signal Multi-purpose Multi-purpose Control signal Control signal Control signal Inter-PFU signal Inter-slice signal Inter-slice signal Data signals Data signals Data signals Data signals Inter-PFU signal Signal Names A0, B0, C0, D0 A1, B1, C1, D1 M0 M1 CE LSR CLK FCI FXA FXB F0, F1 Q0, Q1 OFX0 OFX1 FCO Inputs to LUT4 Inputs to LUT4 Multipurpose Input Multipurpose Input Clock Enable Local Set/Reset System Clock Fast Carry-In1 Intermediate signal to generate LUT6 and LUT7 Intermediate signal to generate LUT6 and LUT7 LUT4 output register bypass signals Register outputs Output of a LUT5 MUX Output of a LUT6, LUT7, LUT82 MUX depending on the slice Slice 2 of each PFU is the fast carry chain output1 Description 1. See Figure 2-3 for connection details. 2. Requires two PFUs. 2-4 Lattice Semiconductor Modes of Operation Architecture LatticeXP2 Family Data Sheet Each slice has up to four potential modes of operation: Logic, Ripple, RAM and ROM. Logic Mode In this mode, the LUTs in each slice are configured as LUT4s. A LUT4 has 16 possible input combinations. Fourinput logic functions are generated by programming the LUT4. Since there are two LUT4s per slice, a LUT5 can be constructed within one slice. Larger LUTs such as LUT6, LUT7 and LUT8, can be constructed by concatenating two or more slices. Note that a LUT8 requires more than four slices. Ripple Mode Ripple mode allows efficient implementation of small arithmetic functions. In ripple mode, the following functions can be implemented by each slice: * Addition 2-bit * Subtraction 2-bit * Add/Subtract 2-bit using dynamic control * Up counter 2-bit * Down counter 2-bit * Up/Down counter with async clear * Up/Down counter with preload (sync) * Ripple mode multiplier building block * Multiplier support * Comparator functions of A and B inputs - A greater-than-or-equal-to B - A not-equal-to B - A less-than-or-equal-to B Two carry signals, FCI and FCO, are generated per slice in this mode, allowing fast arithmetic functions to be constructed by concatenating slices. RAM Mode In this mode, a 16x4-bit distributed Single Port RAM (SPR) can be constructed using each LUT block in Slice 0 and Slice 2 as a 16x1-bit memory. Slice 1 is used to provide memory address and control signals. A 16x2-bit Pseudo Dual Port RAM (PDPR) memory is created by using one slice as the read-write port and the other companion slice as the read-only port. The Lattice design tools support the creation of a variety of different size memories. Where appropriate, the software will construct these using distributed memory primitives that represent the capabilities of the PFU. Table 2-3 shows the number of slices required to implement different distributed RAM primitives. For more information on using RAM in LatticeXP2 devices, please see TN1137, LatticeXP2 Memory Usage Guide. Table 2-3. Number of Slices Required For Implementing Distributed RAM SPR 16X4 Number of slices 3 Note: SPR = Single Port RAM, PDPR = Pseudo Dual Port RAM PDPR 16X4 3 ROM Mode ROM mode uses the LUT logic; hence, Slices 0 through 3 can be used in the ROM mode. Preloading is accomplished through the programming interface during PFU configuration. 2-5 Lattice Semiconductor Architecture LatticeXP2 Family Data Sheet Routing There are many resources provided in the LatticeXP2 devices to route signals individually or as busses with related control signals. The routing resources consist of switching circuitry, buffers and metal interconnect (routing) segments. The inter-PFU connections are made with x1 (spans two PFU), x2 (spans three PFU) or x6 (spans seven PFU) connections. The x1 and x2 connections provide fast and efficient connections in horizontal and vertical directions. The x2 and x6 resources are buffered to allow both short and long connections routing between PFUs. The LatticeXP2 family has an enhanced routing architecture to produce a compact design. The ispLEVER design tool takes the output of the synthesis tool and places and routes the design. Generally, the place and route tool is completely automatic, although an interactive routing editor is available to optimize the design. sysCLOCK Phase Locked Loops (PLL) The sysCLOCK PLLs provide the ability to synthesize clock frequencies. The LatticeXP2 family supports between two and four full featured General Purpose PLLs (GPLL). The architecture of the GPLL is shown in Figure 2-4. CLKI, the PLL reference frequency, is provided either from the pin or from routing; it feeds into the Input Clock Divider block. CLKFB, the feedback signal, is generated from CLKOP (the primary clock output) or from a user clock pin/logic. CLKFB feeds into the Feedback Divider and is used to multiply the reference frequency. Both the input path and feedback signals enter the Voltage Controlled Oscillator (VCO) block. The phase and frequency of the VCO are determined from the input path and feedback signals. A LOCK signal is generated by the VCO to indicate that the VCO is locked with the input clock signal. The output of the VCO feeds into the CLKOP Divider, a post-scalar divider. The duty cycle of the CLKOP Divider output can be fine tuned using the Duty Trim block, which creates the CLKOP signal. By allowing the VCO to operate at higher frequencies than CLKOP, the frequency range of the GPLL is expanded. The output of the CLKOP Divider is passed through the CLKOK Divider, a secondary clock divider, to generate lower frequencies for the CLKOK output. For applications that require even lower frequencies, the CLKOP signal is passed through a divideby-three divider to produce the CLKOK2 output. The CLKOK2 output is provided for applications that use source synchronous logic. The Phase/Duty Cycle/Duty Trim block is used to adjust the phase and duty cycle of the CLKOP Divider output to generate the CLKOS signal. The phase/duty cycle setting can be pre-programmed or dynamically adjusted. The clock outputs from the GPLL; CLKOP, CLKOK, CLKOK2 and CLKOS, are fed to the clock distribution network. For further information on the GPLL please see TN1126, LatticeXP2 sysCLOCK PLL Design and Usage Guide. 2-6 Lattice Semiconductor Figure 2-4. General Purpose PLL (GPLL) Diagram WRDEL DDUTY DPHASE Architecture LatticeXP2 Family Data Sheet 3 Phase/ Duty Cycle/ Duty Trim PFD CLKFB CLKFB Divider VCO/ LOOP FILTER CLKOP Divider Duty Trim CLKOK2 CLKOS CLKI CLKI Divider CLKOP CLKOK CLKOK Divider Lock Detect LOCK Internal Feedback RSTK RST Table 2-4 provides a description of the signals in the GPLL blocks. Table 2-4. GPLL Block Signal Descriptions Signal CLKI CLKFB RST RSTK DPHASE [3:0] DDDUTY [3:0] WRDEL CLKOS CLKOP CLKOK CLKOK2 LOCK I/O I I I I I I I O O O O O Clock input from external pin or routing PLL feedback input from CLKOP (PLL internal), from clock net (CLKOP) or from a user clock (PIN or logic) "1" to reset PLL counters, VCO, charge pumps and M-dividers "1" to reset K-divider DPA Phase Adjust input DPA Duty Cycle Select input DPA Fine Delay Adjust input PLL output clock to clock tree (phase shifted/duty cycle changed) PLL output clock to clock tree (no phase shift) PLL output to clock tree through secondary clock divider PLL output to clock tree (CLKOP divided by 3) "1" indicates PLL LOCK to CLKI Description Clock Dividers LatticeXP2 devices have two clock dividers, one on the left side and one on the right side of the device. These are intended to generate a slower-speed system clock from a high-speed edge clock. The block operates in a /2, /4 or /8 mode and maintains a known phase relationship between the divided down clock and the high-speed clock based on the release of its reset signal. The clock dividers can be fed from the CLKOP output from the GPLLs or from the Edge Clocks (ECLK). The clock divider outputs serve as primary clock sources and feed into the clock distribution network. The Reset (RST) control signal resets the input and forces all outputs to low. The RELEASE signal releases outputs to the input clock. For further information on clock dividers, please see TN1126, sysCLOCK PLL Design and Usage Guide. Figure 2-5 shows the clock divider connections. 2-7 Lattice Semiconductor Figure 2-5. Clock Divider Connections Architecture LatticeXP2 Family Data Sheet ECLK /1 CLKOP (GPLL) /2 CLKDIV /4 RST RELEASE /8 Clock Distribution Network LatticeXP2 devices have eight quadrant-based primary clocks and between six and eight flexible region-based secondary clocks/control signals. Two high performance edge clocks are available on each edge of the device to support high speed interfaces. The clock inputs are selected from external I/Os, the sysCLOCK PLLs, or routing. Clock inputs are fed throughout the chip via the primary, secondary and edge clock networks. Primary Clock Sources LatticeXP2 devices derive primary clocks from four sources: PLL outputs, CLKDIV outputs, dedicated clock inputs and routing. LatticeXP2 devices have two to four sysCLOCK PLLs, located in the four corners of the device. There are eight dedicated clock inputs, two on each side of the device. Figure 2-6 shows the primary clock sources. 2-8 Lattice Semiconductor Figure 2-6. Primary Clock Sources for XP2-17 Clock Input Clock Input From Routing Architecture LatticeXP2 Family Data Sheet PLL Input GPLL GPLL PLL Input CLK DIV CLK DIV Clock Input Primary Clock Sources to Eight Quadrant Clock Selection Clock Input Clock Input Clock Input PLL Input GPLL GPLL PLL Input From Routing Clock Input Clock Input Note: This diagram shows sources for the XP2-17 device. Smaller LatticeXP2 devices have two GPLLs. 2-9 Lattice Semiconductor Secondary Clock/Control Sources Architecture LatticeXP2 Family Data Sheet LatticeXP2 devices derive secondary clocks (SC0 through SC7) from eight dedicated clock input pads and the rest from routing. Figure 2-7 shows the secondary clock sources. Figure 2-7. Secondary Clock Sources Clock Input Clock Input From Routing From Routing From Routing From Routing From Routing From Routing From Routing From Routing Clock Input Clock Input Secondary Clock Sources Clock Input Clock Input From Routing From Routing From Routing From Routing From Routing From Routing Clock Input Clock Input From Routing From Routing 2-10 Lattice Semiconductor Edge Clock Sources Architecture LatticeXP2 Family Data Sheet Edge clock resources can be driven from a variety of sources at the same edge. Edge clock resources can be driven from adjacent edge clock PIOs, primary clock PIOs, PLLs and clock dividers as shown in Figure 2-8. Figure 2-8. Edge Clock Sources Clock Input From Routing Clock Input From Routing Sources for top edge clocks CLKOP CLKOP CLKOS GPLL PLL Input GPLL CLKOS PLL Input From Routing Clock Input Clock Input From Routing CLKOP CLKOP CLKOS GPLL From Routing Clock Input Clock Input From Routing Eight Edge Clocks (ECLK) Two Clocks per Edge PLL Input GPLL CLKOS PLL Input Sources for left edge clocks Sources for bottom edge clocks From Routing Clock Input Clock Input From Routing Sources for right edge clocks Note: This diagram shows sources for the XP2-17 device. Smaller LatticeXP2 devices have two GPLLs. 2-11 Lattice Semiconductor Primary Clock Routing Architecture LatticeXP2 Family Data Sheet The clock routing structure in LatticeXP2 devices consists of a network of eight primary clock lines (CLK0 through CLK7) per quadrant. The primary clocks of each quadrant are generated from muxes located in the center of the device. All the clock sources are connected to these muxes. Figure 2-9 shows the clock routing for one quadrant. Each quadrant mux is identical. If desired, any clock can be routed globally. Figure 2-9. Per Quadrant Primary Clock Selection Primary Clock Sources: PLLs + CLKDIVs + PIOs + Routing 30:1 30:1 30:1 30:1 30:1 30:1 29:1 29:1 29:1 29:1 DCS CLK0 CLK1 CLK2 CLK3 CLK4 CLK5 CLK6 DCS CLK7 8 Primary Clocks (CLK0 to CLK7) per Quadrant Dynamic Clock Select (DCS) The DCS is a smart multiplexer function available in the primary clock routing. It switches between two independent input clock sources without any glitches or runt pulses. This is achieved irrespective of when the select signal is toggled. There are two DCS blocks per quadrant; in total, eight DCS blocks per device. The inputs to the DCS block come from the center muxes. The output of the DCS is connected to primary clocks CLK6 and CLK7 (see Figure 29). Figure 2-10 shows the timing waveforms of the default DCS operating mode. The DCS block can be programmed to other modes. For more information on the DCS, please see TN1126, LatticeXP2 sysCLOCK PLL Design and Usage Guide. Figure 2-10. DCS Waveforms CLK0 CLK1 SEL DCSOUT Secondary Clock/Control Routing Secondary clocks in the LatticeXP2 devices are region-based resources. The benefit of region-based resources is the relatively low injection delay and skew within the region, as compared to primary clocks. EBR rows, DSP rows and a special vertical routing channel bound the secondary clock regions. This special vertical routing channel aligns with either the left edge of the center DSP block in the DSP row or the center of the DSP row. Figure 2-11 shows this special vertical routing channel and the eight secondary clock regions for the LatticeXP2-40. 2-12 Lattice Semiconductor Architecture LatticeXP2 Family Data Sheet LatticeXP2-30 and smaller devices have six secondary clock regions. All devices in the LatticeXP2 family have four secondary clocks (SC0 to SC3) which are distributed to every region. The secondary clock muxes are located in the center of the device. Figure 2-12 shows the mux structure of the secondary clock routing. Secondary clocks SC0 to SC3 are used for clock and control and SC4 to SC7 are used for high fan-out signals. Figure 2-11. Secondary Clock Regions XP2-40 I/O Bank 0 I/O Bank 1 Vertical Routing Channel Regional Boundary Secondary Clock Region 1 Secondary Clock Region 5 EBR Row Regional Boundary I/O Bank 2 I/O Bank 7 Secondary Clock Region 2 Secondary Clock Region 6 I/O Bank 6 Secondary Clock Region 3 Secondary Clock Region 7 EBR Row Regional Boundary I/O Bank 3 Secondary Clock Region 4 Secondary Clock Region 8 DSP Row Regional Boundary I/O Bank 5 I/O Bank 4 2-13 Lattice Semiconductor Figure 2-12. Secondary Clock Selection Architecture LatticeXP2 Family Data Sheet Secondary Clock Feedlines: 8 PIOs + 16 Routing 24:1 24:1 24:1 24:1 24:1 24:1 24:1 24:1 SC0 SC1 SC2 SC3 SC4 SC5 SC6 SC7 4 Secondary Clocks/CE/LSR (SC0 to SC3) per Region Clock/Control 4 High Fan-out Data Signals (SC4 to SC7) per Region High Fan-out Data Slice Clock Selection Figure 2-13 shows the clock selections and Figure 2-14 shows the control selections for Slice0 through Slice2. All the primary clocks and the four secondary clocks are routed to this clock selection mux. Other signals, via routing, can be used as clock inputs to the slices. Slice controls are generated from the secondary clocks or other signals connected via routing. If none of the signals are selected for both clock and control, then the default value of the mux output is 1. Slice 3 does not have any registers; therefore it does not have the clock or control muxes. Figure 2-13. Slice0 through Slice2 Clock Selection Primary Clock 8 Secondary Clock 4 Routing 12 Vcc 1 Clock to Slice 25:1 2-14 Lattice Semiconductor Figure 2-14. Slice0 through Slice2 Control Selection Architecture LatticeXP2 Family Data Sheet Secondary Clock 3 Slice Control Routing 12 Vcc 1 16:1 Edge Clock Routing LatticeXP2 devices have eight high-speed edge clocks that are intended for use with the PIOs in the implementation of high-speed interfaces. Each device has two edge clocks per edge. Figure 2-15 shows the selection muxes for these clocks. Figure 2-15. Edge Clock Mux Connections Top and Bottom Edge Clocks ECLK1/ ECLK2 (Both Muxes) Routing Clock Input Pad Input Pad GPLL Input Pad Left and Right Edge Clocks ECLK1 GPLL Output CLKOP Routing Input Pad GPLL Input Pad Left and Right Edge Clocks ECLK2 GPLL Output CLKOS Routing 2-15 Lattice Semiconductor Architecture LatticeXP2 Family Data Sheet sysMEM Memory LatticeXP2 devices contains a number of sysMEM Embedded Block RAM (EBR). The EBR consists of 18 Kbit RAM with dedicated input and output registers. sysMEM Memory Block The sysMEM block can implement single port, dual port or pseudo dual port memories. Each block can be used in a variety of depths and widths as shown in Table 2-5. FIFOs can be implemented in sysMEM EBR blocks by using support logic with PFUs. The EBR block supports an optional parity bit for each data byte to facilitate parity checking. EBR blocks provide byte-enable support for configurations with18-bit and 36-bit data widths. Table 2-5. sysMEM Block Configurations Memory Mode Configurations 16,384 x 1 8,192 x 2 4,096 x 4 2,048 x 9 1,024 x 18 512 x 36 16,384 x 1 8,192 x 2 4,096 x 4 2,048 x 9 1,024 x 18 16,384 x 1 8,192 x 2 4,096 x 4 2,048 x 9 1,024 x 18 512 x 36 Single Port True Dual Port Pseudo Dual Port Bus Size Matching All of the multi-port memory modes support different widths on each of the ports. The RAM bits are mapped LSB word 0 to MSB word 0, LSB word 1 to MSB word 1, and so on. Although the word size and number of words for each port varies, this mapping scheme applies to each port. FlashBAK EBR Content Storage All the EBR memory in the LatticeXP2 is shadowed by Flash memory. Optionally, initialization values for the memory blocks can be defined using the Lattice ispLEVER tools. The initialization values are loaded into the Flash memory during device programming and into the SRAM at power up or whenever the device is reconfigured. This feature is ideal for the storage of a variety of information such as look-up tables and microprocessor code. It is also possible to write the current contents of the EBR memory back to Flash memory. This capability is useful for the storage of data such as error codes and calibration information. For additional information on the FlashBAK capability see TN1137, LatticeXP2 Memory Usage Guide. 2-16 Lattice Semiconductor Figure 2-16. FlashBAK Technology Make Infinite Reads and Writes to EBR Architecture LatticeXP2 Family Data Sheet Write to Flash During Programming Flash JTAG / SPI Port FPGA Logic EBR Write From Flash to EBR During Configuration / Write From EBR to Flash on User Command Memory Cascading Larger and deeper blocks of RAMs can be created using EBR sysMEM Blocks. Typically, the Lattice design tools cascade memory transparently, based on specific design inputs. Single, Dual and Pseudo-Dual Port Modes In all the sysMEM RAM modes the input data and address for the ports are registered at the input of the memory array. The output data of the memory is optionally registered at the output. EBR memory supports two forms of write behavior for single port or dual port operation: 1. Normal - Data on the output appears only during a read cycle. During a write cycle, the data (at the current address) does not appear on the output. This mode is supported for all data widths. 2. Write Through - A copy of the input data appears at the output of the same port during a write cycle. This mode is supported for all data widths. Memory Core Reset The memory array in the EBR utilizes latches at the A and B output ports. These latches can be reset asynchronously or synchronously. RSTA and RSTB are local signals, which reset the output latches associated with Port A and Port B respectively. GSRN, the global reset signal, resets both ports. The output data latches and associated resets for both ports are as shown in Figure 2-17. Figure 2-17. Memory Core Reset Memory Core D SET Q Port A[17:0] LCLR Output Data Latches D SET Q Port B[17:0] LCLR RSTA RSTB GSRN Programmable Disable 2-17 Lattice Semiconductor Architecture LatticeXP2 Family Data Sheet For further information on the sysMEM EBR block, please see TN1137, LatticeXP2 Memory Usage Guide. EBR Asynchronous Reset EBR asynchronous reset or GSR (if used) can only be applied if all clock enables are low for a clock cycle before the reset is applied and released a clock cycle after the low-to-high transition of the reset signal, as shown in Figure 2-18. The GSR input to the EBR is always asynchronous. Figure 2-18. EBR Asynchronous Reset (Including GSR) Timing Diagram Reset Clock Clock Enable If all clock enables remain enabled, the EBR asynchronous reset or GSR may only be applied and released after the EBR read and write clock inputs are in a steady state condition for a minimum of 1/fMAX (EBR clock). The reset release must adhere to the EBR synchronous reset setup time before the next active read or write clock edge. If an EBR is pre-loaded during configuration, the GSR input must be disabled or the release of the GSR during device Wake Up must occur before the release of the device I/Os becoming active. These instructions apply to all EBR RAM and ROM implementations. Note that there are no reset restrictions if the EBR synchronous reset is used and the EBR GSR input is disabled. sysDSPTM Block The LatticeXP2 family provides a sysDSP block making it ideally suited for low cost, high performance Digital Signal Processing (DSP) applications. Typical functions used in these applications include Bit Correlators, Fast Fourier Transform (FFT) functions, Finite Impulse Response (FIR) Filter, Reed-Solomon Encoder/Decoder, Turbo Encoder/ Decoder and Convolutional Encoder/Decoder. These complex signal processing functions use similar building blocks such as multiply-adders and multiply-accumulators. sysDSP Block Approach Compare to General DSP Conventional general-purpose DSP chips typically contain one to four (Multiply and Accumulate) MAC units with fixed data-width multipliers; this leads to limited parallelism and limited throughput. Their throughput is increased by higher clock speeds. The LatticeXP2 family, on the other hand, has many DSP blocks that support different datawidths. This allows the designer to use highly parallel implementations of DSP functions. The designer can optimize the DSP performance vs. area by choosing appropriate levels of parallelism. Figure 2-19 compares the fully serial and the mixed parallel and serial implementations. 2-18 Lattice Semiconductor Figure 2-19. Comparison of General DSP and LatticeXP2 Approaches Architecture LatticeXP2 Family Data Sheet Operand A Operand A Operand B Operand B Operand A Operand B Operand A Operand B Single Multiplier x M loops x Multiplier 0 Multiplier 1 x (k adds) x + Output m/k loops Multiplier k Accumulator Function implemented in General purpose DSP m/k accumulate Function implemented in LatticeXP2 sysDSP Block Capabilities The sysDSP block in the LatticeXP2 family supports four functional elements in three 9, 18 and 36 data path widths. The user selects a function element for a DSP block and then selects the width and type (signed/unsigned) of its operands. The operands in the LatticeXP2 family sysDSP Blocks can be either signed or unsigned but not mixed within a function element. Similarly, the operand widths cannot be mixed within a block. DSP elements can be concatenated. The resources in each sysDSP block can be configured to support the following four elements: * MULT (Multiply) * MAC (Multiply, Accumulate) * MULTADDSUB (Multiply, Addition/Subtraction) * MULTADDSUBSUM (Multiply, Addition/Subtraction, Accumulate) The number of elements available in each block depends on the width selected from the three available options: x9, x18, and x36. A number of these elements are concatenated for highly parallel implementations of DSP functions. Table 2-6 shows the capabilities of the block. Table 2-6. Maximum Number of Elements in a Block Width of Multiply MULT MAC MULTADDSUB MULTADDSUBSUM x9 8 2 4 2 x18 4 2 2 1 x36 1 -- -- -- Some options are available in four elements. The input register in all the elements can be directly loaded or can be loaded as shift register from previous operand registers. By selecting `dynamic operation' the following operations are possible: 2-19 Lattice Semiconductor Architecture LatticeXP2 Family Data Sheet * In the `Signed/Unsigned' options the operands can be switched between signed and unsigned on every cycle. * In the `Add/Sub' option the Accumulator can be switched between addition and subtraction on every cycle. * The loading of operands can switch between parallel and serial operations. MULT sysDSP Element This multiplier element implements a multiply with no addition or accumulator nodes. The two operands, A and B, are multiplied and the result is available at the output. The user can enable the input/output and pipeline registers. Figure 2-20 shows the MULT sysDSP element. Figure 2-20. MULT sysDSP Element Shift Register B In Multiplicand m Shift Register A In m m Multiplier n n n Output Register Input Data Register A m Multiplier Input Data Register B m n n x Pipeline Register m+n (default) m+n Output Signed A Signed B Input Register Input Register To Multiplier To Multiplier CLK (CLK0,CLK1,CLK2,CLK3) CE (CE0,CE1,CE2,CE3) RST(RST0,RST1,RST2,RST3) Shift Register B Out Shift Register A Out 2-20 Lattice Semiconductor MAC sysDSP Element Architecture LatticeXP2 Family Data Sheet In this case, the two operands, A and B, are multiplied and the result is added with the previous accumulated value. This accumulated value is available at the output. The user can enable the input and pipeline registers but the output register is always enabled. The output register is used to store the accumulated value. The Accumulators in the DSP blocks in LatticeXP2 family can be initialized dynamically. A registered overflow signal is also available. The overflow conditions are provided later in this document. Figure 2-21 shows the MAC sysDSP element. Figure 2-21. MAC sysDSP Serial Register B in Multiplicand m Serial Register A in m Accumulator Preload n Input Data Register A m Multiplier Input Data Register B n n n Signed A Signed B Addn Accumsload Input Register Input Register Input Register Input Register Pipeline Register Pipeline Register Pipeline Register Pipeline Register Output Register m+n (default) Pipeline Register x Output Register Multiplier n n m m+n+16 (default) Output m+n+16 (default) To Accumulator To Accumulator To Accumulator Overflow signal CLK (CLK0,CLK1,CLK2,CLK3) To Accumulator CE (CE0,CE1,CE2,CE3) RST(RST0,RST1,RST2,RST3) SROB SROA 2-21 Lattice Semiconductor MULTADDSUB sysDSP Element Architecture LatticeXP2 Family Data Sheet In this case, the operands A0 and B0 are multiplied and the result is added/subtracted with the result of the multiplier operation of operands A1 and B1. The user can enable the input, output and pipeline registers. Figure 2-22 shows the MULTADDSUB sysDSP element. Figure 2-22. MULTADDSUB Shift Register B In Multiplicand A0 n n Input Data Register B n m m Input Data Register A m Multiplier Shift Register A In m CLK (CLK0,CLK1,CLK2,CLK3) CE (CE0,CE1,CE2,CE3) Multiplier B0 n RST (RST0,RST1,RST2,RST3) n m m m x Pipeline Register m+n (default) Add/Sub Multiplicand A1 Output Register Output m+n+1 (default) Multiplier B1 n n m+n+1 (default) m Multiplier m+n (default) Input Data Register A Input Data Register B n m Pipeline Pipe Register Reg Pipeline Pipe Register Reg Pipeline Pipe Register Reg x Pipeline Register Signed A Signed B Addn n Input Register Input Register Input Register To Add/Sub To Add/Sub To Add/Sub Shift Register B Out Shift Register A Out 2-22 Lattice Semiconductor MULTADDSUBSUM sysDSP Element Architecture LatticeXP2 Family Data Sheet In this case, the operands A0 and B0 are multiplied and the result is added/subtracted with the result of the multiplier operation of operands A1 and B1. Additionally the operands A2 and B2 are multiplied and the result is added/ subtracted with the result of the multiplier operation of operands A3 and B3. The result of both addition/subtraction are added in a summation block. The user can enable the input, output and pipeline registers. Figure 2-23 shows the MULTADDSUBSUM sysDSP element. Figure 2-23. MULTADDSUBSUM Shift Register B In Multiplicand A0 Multiplier B0 n n Input Data Register B n m m Input Data Register A m Multiplier Shift Register A In m CLK (CLK0,CLK1,CLK2,CLK3) CE (CE0,CE1,CE2,CE3) n m m m Input Data Register A n x Pipeline Register m+n (default) RST(RST0,RST1,RST2,RST3) Add/Sub0 Multiplicand A1 Multiplier B1 n m+n (default) Multiplier n n Input Data Register B n x Pipeline Register m+n+1 SUM Output Register Multiplicand A2 Multiplier B2 n n Input Data Register B m m m m+n+2 Output m+n+2 n Input Data Register A m Multiplier n m m m Input Data Register A m x Pipeline Register m+n (default) m+n+1 Add/Sub1 Multiplicand A3 Multiplier B3 n m+n (default) Multiplier n n Input Data Register B n m Input Register Input Register Input Register Input Register Pipeline Register Pipeline Register Pipeline Register Pipeline Register x Pipeline Register Signed A Signed B Addn0 Addn1 n To Add/Sub0, Add/Sub1 To Add/Sub0, Add/Sub1 To Add/Sub0 To Add/Sub1 Shift Register B Out Shift Register A Out Clock, Clock Enable and Reset Resources Global Clock, Clock Enable (CE) and Reset (RST) signals from routing are available to every DSP block. From four clock sources (CLK0, CLK1, CLK2, CLK3) one clock is selected for each input register, pipeline register and output 2-23 Lattice Semiconductor Architecture LatticeXP2 Family Data Sheet register. Similarly, CE and RST are selected from their four respective sources (CE0, CE1, CE2, CE3 and RST0, RST1, RST2, RST3) at each input register, pipeline register and output register. Signed and Unsigned with Different Widths The DSP block supports other widths, in addition to x9, x18 and x36 widths, of signed and unsigned multipliers. For unsigned operands, unused upper data bits should be filled to create a valid x9, x18 or x36 operand. For signed two's complement operands, sign extension of the most significant bit should be performed until x9, x18 or x36 width is reached. Table 2-7 provides an example of this. Table 2-7. Sign Extension Example Number +5 -6 Unsigned 0101 N/A Unsigned 9-bit 000000101 N/A Unsigned 18-bit 000000000000000101 N/A Signed 0101 1010 Two's Complement Signed 9 Bits 000000101 111111010 Two's Complement Signed 18 Bits 000000000000000101 111111111111111010 OVERFLOW Flag from MAC The sysDSP block provides an overflow output to indicate that the accumulator has overflowed. "Roll-over" occurs and an overflow signal is indicated when any of the following is true: two unsigned numbers are added and the result is a smaller number than the accumulator, two positive numbers are added with a negative sum or two negative numbers are added with a positive sum. Note that when overflow occurs the overflow flag is present for only one cycle. By counting these overflow pulses in FPGA logic, larger accumulators can be constructed. The conditions for the overflow signal for signed and unsigned operands are listed in Figure 2-24. Figure 2-24. Accumulator Overflow/Underflow 011111100 011111101 011111110 011111111 100000000 100000001 100000010 252 253 254 255 256 257 258 000000011 000000010 000000001 000000000 111111111 111111110 111111101 3 2 1 0 511 510 509 Carry signal is generated for one cycle when this boundary is crossed Unsigned Operation Overflow signal is generated for one cycle when this boundary is crossed 011111100 011111101 011111110 011111111 100000000 100000001 100000010 252 253 254 255 -256 -255 -254 000000011 000000010 000000001 000000000 111111111 111111110 111111101 +3 +2 +1 0 -1 -2 -3 Signed Operation 2-24 Lattice Semiconductor IPexpressTM Architecture LatticeXP2 Family Data Sheet The user can access the sysDSP block via the ispLEVER IPexpress tool, which provides the option to configure each DSP module (or group of modules), or by direct HDL instantiation. In addition, Lattice has partnered with The MathWorks(R) to support instantiation in the Simulink(R) tool, a graphical simulation environment. Simulink works with ispLEVER to dramatically shorten the DSP design cycle in Lattice FPGAs. Optimized DSP Functions Lattice provides a library of optimized DSP IP functions. Some of the IP cores planned for the LatticeXP2 DSP include the Bit Correlator, FFT functions, FIR Filter, Reed-Solomon Encoder/Decoder, Turbo Encoder/Decoder and Convolutional Encoder/Decoder. Please contact Lattice to obtain the latest list of available DSP IP cores. Resources Available in the LatticeXP2 Family Table 2-8 shows the maximum number of multipliers for each member of the LatticeXP2 family. Table 2-9 shows the maximum available EBR RAM Blocks and Serial TAG Memory bits in each LatticeXP2 device. EBR blocks, together with Distributed RAM can be used to store variables locally for fast DSP operations. Table 2-8. Maximum Number of DSP Blocks in the LatticeXP2 Family Device XP2-5 XP2-8 XP2-17 XP2-30 XP2-40 DSP Block 3 4 5 7 8 9x9 Multiplier 24 32 40 56 64 18x18 Multiplier 12 16 20 28 32 36x36 Multiplier 3 4 5 7 8 Table 2-9. Embedded SRAM/TAG Memory in the LatticeXP2 Family Device XP2-5 XP2-8 XP2-17 XP2-30 XP2-40 EBR SRAM Block 9 12 15 21 48 Total EBR SRAM (Kbits) 166 221 276 387 885 TAG Memory (Bits) 632 768 2184 2640 3384 LatticeXP2 DSP Performance Table 2-10 lists the maximum performance in Millions of MAC (MMAC) operations per second for each member of the LatticeXP2 family. Table 2-10. DSP Performance Device XP2-5 XP2-8 XP2-17 XP2-30 XP2-40 DSP Block 3 4 5 7 8 DSP Performance MMAC 3,900 5,200 6,500 9,100 10,400 For further information on the sysDSP block, please see TN1140, LatticeXP2 sysDSP Usage Guide. 2-25 Lattice Semiconductor Architecture LatticeXP2 Family Data Sheet Programmable I/O Cells (PIC) Each PIC contains two PIOs connected to their respective sysIO buffers as shown in Figure 2-25. The PIO Block supplies the output data (DO) and the tri-state control signal (TO) to the sysIO buffer and receives input from the buffer. Table 2-11 provides the PIO signal list. Figure 2-25. PIC Diagram PIOA TD OPOS1 ONEG1 IOLT0 Tristate Register Block OPOS0 OPOS21 ONEG0 ONEG21 PADA "T" IOLD0 Output Register Block sysIO Buffer QNEG01 QNEG11 QPOS01 QPOS11 INCK2 INDD INFF IPOS0 IPOS1 CLK CE LSR GSRN ECLK1 ECLK2 DDRCLKPOL1 DQSXFER1 DQS DEL Control Muxes CLK1 CEO LSR GSR CLK0 CEI Input Register Block DI PADB "C" PIOB 1. Signals are available on left/right/bottom edges only. 2. Selected blocks. Two adjacent PIOs can be joined to provide a differential I/O pair (labeled as "T" and "C") as shown in Figure 2-25. The PAD Labels "T" and "C" distinguish the two PIOs. Approximately 50% of the PIO pairs on the left and right edges of the device can be configured as true LVDS outputs. All I/O pairs can operate as inputs. 2-26 Lattice Semiconductor Table 2-11. PIO Signal List Name CE CLK ECLK1, ECLK2 LSR GSRN INCK2 DQS INDD INFF IPOS0, IPOS1 QPOS0 , QPOS1 1 1 Architecture LatticeXP2 Family Data Sheet Type Control from the core Control from the core Control from the core Control from the core Control from routing Input to the core Input to PIO Input to the core Input to the core Input to the core Input to the core Input to the core Output data from the core Tristate control from the core Control from the core Tristate control from the core Control from core Description Clock enables for input and output block flip-flops System clocks for input and output blocks Fast edge clocks Local Set/Reset Global Set/Reset (active low) Input to Primary Clock Network or PLL reference inputs DQS signal from logic (routing) to PIO Unregistered data input to core Registered input on positive edge of the clock (CLK0) Double data rate registered inputs to the core Gearbox pipelined inputs to the core Gearbox pipelined inputs to the core Output signals from the core for SDR and DDR operation Signals to Tristate Register block for DDR operation Dynamic input delay control bits Tristate signal from the core used in SDR operation Controls signal to the Output block QNEG01, QNEG11 OPOS0, ONEG0, OPOS2, ONEG2 OPOS1 ONEG1 DEL[3:0] TD DDRCLKPOL DQSXFER Control from clock polarity bus Controls the polarity of the clock (CLK0) that feed the DDR input block 1. Signals available on left/right/bottom only. 2. Selected I/O. PIO The PIO contains four blocks: an input register block, output register block, tristate register block and a control logic block. These blocks contain registers for operating in a variety of modes along with necessary clock and selection logic. Input Register Block The input register blocks for PIOs contain delay elements and registers that can be used to condition high-speed interface signals, such as DDR memory interfaces and source synchronous interfaces, before they are passed to the device core. Figure 2-26 shows the diagram of the input register block. Input signals are fed from the sysIO buffer to the input register block (as signal DI). If desired, the input signal can bypass the register and delay elements and be used directly as a combinatorial signal (INDD), a clock (INCK) and, in selected blocks, the input to the DQS delay block. If an input delay is desired, designers can select either a fixed delay or a dynamic delay DEL[3:0]. The delay, if selected, reduces input register hold time requirements when using a global clock. The input block allows three modes of operation. In the Single Data Rate (SDR) mode, the data is registered, by one of the registers in the SDR Sync register block, with the system clock. In DDR mode two registers are used to sample the data on the positive and negative edges of the DQS signal which creates two data streams, D0 and D2. D0 and D2 are synchronized with the system clock before entering the core. Further information on this topic can be found in the DDR Memory Support section of this data sheet. By combining input blocks of the complementary PIOs and sharing registers from output blocks, a gearbox function can be implemented, that takes a double data rate signal applied to PIOA and converts it as four data streams, IPOS0A, IPOS1A, IPOS0B and IPOS1B. Figure 2-26 shows the diagram using this gearbox function. For more information on this topic, please see TN1138, LatticeXP2 High Speed I/O Interface. 2-27 Lattice Semiconductor Architecture LatticeXP2 Family Data Sheet The signal DDRCLKPOL controls the polarity of the clock used in the synchronization registers. It ensures adequate timing when data is transferred from the DQS to system clock domain. For further discussion on this topic, see the DDR Memory section of this data sheet. Figure 2-26. Input Register Block DI (From sysIO Buffer) Fixed Delay Dynamic Delay 0 0 1 INCK2 To DQS Delay Block2 INDD DDR Registers SDR & Sync Registers Clock Transfer Registers IPOS0A D Q QPOS0A D0 D Q D Q 1 DEL [3:0] D-Type /LATCH D-Type1 D-Type From Routing D Q D1 D Q D2 D Q D Q IPOS1A QPOS1A Delayed DQS 0 1 D-Type D-Type D-Type /LATCH D-Type1 To Routing CLK0 (of PIO A) DDRCLKPOL CLKA True PIO (A) in LVDS I/O Pair Comp PIO (B) in LVDS I/O Pair DI (From sysIO Buffer) DDRSRC DDR Registers 0 1 INCK2 To DQS Delay Block2 INDD SDR & Sync Registers 0 1 Fixed Delay Dynamic Delay 0 Clock Transfer Registers D0 IPOS0B QPOS0B D Q 1 D Q DEL [3:0] D-Type D-Type /LATCH D Q D-Type1 From Routing Delayed DQS 0 1 IPOS1B D Q D1 0 D Q D2 1 D Q D Q QPOS1B D-Type D-Type D-Type /LATCH D-Type1 To Routing CLK0 (of PIO B) DDRCLKPOL CLKB 1. Shared with output register 2. Selected PIO. Gearbox Configuration Bit Note: Simplified version does not show CE and SET/RESET details Output Register Block The output register block provides the ability to register signals from the core of the device before they are passed to the sysIO buffers. The blocks on the PIOs on the left, right and bottom contain registers for SDR operation that are combined with an additional latch for DDR operation. Figure 2-27 shows the diagram of the Output Register Block for PIOs. In SDR mode, ONEG0 feeds one of the flip-flops that then feeds the output. The flip-flop can be configured as a Dtype or latch. In DDR mode, ONEG0 and OPOS0 are fed into registers on the positive edge of the clock. At the next clock cycle the registered OPOS0 is latched. A multiplexer running off the same clock cycle selects the correct register to feed the output (D0). By combining output blocks of the complementary PIOs and sharing some registers from input blocks, a gearbox function can be implemented, to take four data streams ONEG0A, ONEG1A, ONEG1B and ONEG1B. Figure 2-27 2-28 Lattice Semiconductor Architecture LatticeXP2 Family Data Sheet shows the diagram using this gearbox function. For more information on this topic, see TN1138, LatticeXP2 High Speed I/O Interface. Figure 2-27. Output and Tristate Block TD Tristate Logic ONEG1 D Q D-Type /LATCH 0 1 0 0 1 TO OPOS1 D Q D Q Latch 1 D-Type To sysIO Buffer From Routing 0 ONEG0 D Q 0 1 D-Type* 1 D Q D-Type /LATCH DDR Output Registers DO 0 0 1 OPOS0 Q D D-Type* D Latch Q 0 1 0 D 1 Q D Latch Q 1 D-Type CLKA ECLK1 ECLK2 CLK1 (CLKA) DQSXFER Clock Transfer Registers 0 1 0 1 Programmable Control Output Logic True PIO (A) in LVDS I/O Pair Comp PIO (B) in LVDS I/O Pair TD Tristate Logic ONEG1 Q D D-Type /LATCH 0 1 0 0 1 TO OPOS1 D Q D Q Latch 1 D-Type To sysIO Buffer From Routing ONEG0 D Q D-Type* Q D D-Type /LATCH DDR Output Registers 0 1 DO 0 OPOS0 D Q D Latch Q D Q D Latch Q 1 D-Type* D-Type CLKB ECLK1 ECLK2 CLK1 (CLKB) DQSXFER Clock Transfer Registers 0 1 0 1 Programmable Control Output Logic * Shared with input register Note: Simplified version does not show CE and SET/RESET details 2-29 Lattice Semiconductor Tristate Register Block Architecture LatticeXP2 Family Data Sheet The tristate register block provides the ability to register tri-state control signals from the core of the device before they are passed to the sysIO buffers. The block contains a register for SDR operation and an additional latch for DDR operation. Figure 2-27 shows the Tristate Register Block with the Output Block In SDR mode, ONEG1 feeds one of the flip-flops that then feeds the output. The flip-flop can be configured as Dtype or latch. In DDR mode, ONEG1 and OPOS1 are fed into registers on the positive edge of the clock. Then in the next clock the registered OPOS1 is latched. A multiplexer running off the same clock cycle selects the correct register for feeding to the output (D0). Control Logic Block The control logic block allows the selection and modification of control signals for use in the PIO block. A clock signal is selected from general purpose routing, ECLK1, ECLK2 or a DQS signal (from the programmable DQS pin) and is provided to the input register block. The clock can optionally be inverted. DDR Memory Support PICs have additional circuitry to allow implementation of high speed source synchronous and DDR memory interfaces. PICs have registered elements that support DDR memory interfaces. Interfaces on the left and right edges are designed for DDR memories that support 16 bits of data, whereas interfaces on the top and bottom are designed for memories that support 18 bits of data. One of every 16 PIOs on the left and right and one of every 18 PIOs on the top and bottom contain delay elements to facilitate the generation of DQS signals. The DQS signals feed the DQS buses which span the set of 16 or 18 PIOs. Figure 2-28 and Figure 2-29 show the DQS pin assignments in each set of PIOs. The exact DQS pins are shown in a dual function in the Logic Signal Connections table in this data sheet. Additional detail is provided in the Signal Descriptions table. The DQS signal from the bus is used to strobe the DDR data from the memory into input register blocks. For additional information on using DDR memory support please see TN1138, LatticeXP2 High Speed I/O Interface. 2-30 Lattice Semiconductor Figure 2-28. DQS Input Routing (Left and Right) PIO A PIO B PIO A PIO B PIO A PIO B PIO A PIO B PIO A DQS PIO B PIO A PIO B PIO A PIO B PIO A PIO B sysIO Buffer Delay Architecture LatticeXP2 Family Data Sheet PADA "T" LVDS Pair PADB "C" PADA "T" LVDS Pair PADB "C" PADA "T" LVDS Pair PADB "C" PADA "T" LVDS Pair PADB "C" Assigned DQS Pin PADA "T" LVDS Pair PADB "C" PADA "T" LVDS Pair PADB "C" PADA "T" LVDS Pair PADB "C" PADA "T" LVDS Pair PADB "C" Figure 2-29. DQS Input Routing (Top and Bottom) PIO A PIO B PIO A PIO B PIO A PIO B PIO A PIO B PIO A sysIO Buffer Delay PADA "T" LVDS Pair PADB "C" PADA "T" LVDS Pair PADB "C" PADA "T" LVDS Pair PADB "C" PADA "T" LVDS Pair PADB "C" Assigned DQS Pin DQS PIO B PIO A PIO B PIO A PIO B PIO A PIO B PIO A PIO B PADA "T" LVDS Pair PADB "C" PADA "T" LVDS Pair PADB "C" PADA "T" LVDS Pair PADB "C" PADA "T" LVDS Pair PADB "C" PADA "T" LVDS Pair PADB "C" 2-31 Lattice Semiconductor DLL Calibrated DQS Delay Block Architecture LatticeXP2 Family Data Sheet Source synchronous interfaces generally require the input clock to be adjusted in order to correctly capture data at the input register. For most interfaces a PLL is used for this adjustment. However, in DDR memories the clock, referred to as DQS, is not free-running, and this approach cannot be used. The DQS Delay block provides the required clock alignment for DDR memory interfaces. The DQS signal (selected PIOs only, as shown in Figure 2-30) feeds from the PAD through a DQS delay element to a dedicated DQS routing resource. The DQS signal also feeds polarity control logic which controls the polarity of the clock to the sync registers in the input register blocks. Figure 2-30 and Figure 2-31 show how the DQS transition signals are routed to the PIOs. The temperature, voltage and process variations of the DQS delay block are compensated by a set of 6-bit bus calibration signals from two dedicated DLLs (DDR_DLL) on opposite sides of the device. Each DLL compensates DQS delays in its half of the device as shown in Figure 2-30. The DLL loop is compensated for temperature, voltage and process variations by the system clock and feedback loop. Figure 2-30. Edge Clock, DLL Calibration and DQS Local Bus Distribution Spans 16 PIOs Left & Right Sides I/O Bank 0 I/O Bank 1 ECLK1 ECLK2 I/O Bank 2 I/O Bank 7 DQS Input DDR_DLL (Left) DDR_DLL (Right) Delayed DQS Polarity Control I/O Bank 3 DQSXFER DQS Delay Control Bus Spans 18 PIOs Top & Bottom Sides I/O Bank 6 I/O Bank 5 I/O Bank 4 2-32 Lattice Semiconductor Figure 2-31. DQS Local Bus CLK1 ECLK2 ECLK1 Polarity control Architecture LatticeXP2 Family Data Sheet DCNTL[6:0] DQSXFER DQS PIO DQSXFER Output Register Block Input Register Block GSR CEI DQS CLK1 DQS To DDR Reg. sysIO Buffer DDR Datain PAD To Sync Reg. DI PIO Polarity Control Logic DQS DQSDEL Calibration bus from DLL DCNTL[6:0] sysIO Buffer DQS Strobe PAD DI ECLK1 DQSXFER DQSXFERDEL* DCNTL[6:0] *DQSXFERDEL shifts ECLK1 by 90% and is not associated with a particular PIO. Polarity Control Logic In a typical DDR memory interface design, the phase relationship between the incoming delayed DQS strobe and the internal system clock (during the READ cycle) is unknown. The LatticeXP2 family contains dedicated circuits to transfer data between these domains. To prevent set-up and hold violations, at the domain transfer between DQS (delayed) and the system clock, a clock polarity selector is used. This changes the edge on which the data is registered in the synchronizing registers in the input register block and requires evaluation at the start of each READ cycle for the correct clock polarity. Prior to the READ operation in DDR memories, DQS is in tristate (pulled by termination). The DDR memory device drives DQS low at the start of the preamble state. A dedicated circuit detects this transition. This signal is used to control the polarity of the clock to the synchronizing registers. 2-33 Lattice Semiconductor DQSXFER Architecture LatticeXP2 Family Data Sheet LatticeXP2 devices provide a DQSXFER signal to the output buffer to assist it in data transfer to DDR memories that require DQS strobe be shifted 90o. This shifted DQS strobe is generated by the DQSDEL block. The DQSXFER signal runs the span of the data bus. sysIO Buffer Each I/O is associated with a flexible buffer referred to as a sysIO buffer. These buffers are arranged around the periphery of the device in groups referred to as banks. The sysIO buffers allow users to implement the wide variety of standards that are found in today's systems including LVCMOS, SSTL, HSTL, LVDS and LVPECL. sysIO Buffer Banks LatticeXP2 devices have eight sysIO buffer banks for user I/Os arranged two per side. Each bank is capable of supporting multiple I/O standards. Each sysIO bank has its own I/O supply voltage (VCCIO). In addition, each bank has voltage references, VREF1 and VREF2, that allow it to be completely independent from the others. Figure 2-32 shows the eight banks and their associated supplies. In LatticeXP2 devices, single-ended output buffers and ratioed input buffers (LVTTL, LVCMOS and PCI) are powered using VCCIO. LVTTL, LVCMOS33, LVCMOS25 and LVCMOS12 can also be set as fixed threshold inputs independent of VCCIO. Each bank can support up to two separate VREF voltages, VREF1 and VREF2, that set the threshold for the referenced input buffers. Some dedicated I/O pins in a bank can be configured to be a reference voltage supply pin. Each I/O is individually configurable based on the bank's supply and reference voltages. Figure 2-32. LatticeXP2 Banks TOP V CCIO0 V REF1(0) V REF1(1) V REF2(1) V CCIO1 Bank 0 V V REF2(0) GND GND V CCIO2 Bank 1 CCIO7 Bank 7 V REF1(7) V REF2(7) GND V REF1(2) V REF2(2) GND Bank 2 RIGHT LEFT V CCIO6 V CCIO3 Bank 6 V REF1(6) V REF2(6) GND V REF1(3) V REF2(3) GND Bank 3 Bank 5 Bank 4 V CCIO5 VREF1(5) V CCIO4 V REF1(4) V REF2(5) V REF2(4) GND BOTTOM 2-34 GND Lattice Semiconductor LatticeXP2 devices contain two types of sysIO buffer pairs. Architecture LatticeXP2 Family Data Sheet 1. Top and Bottom (Banks 0, 1, 4 and 5) sysIO Buffer Pairs (Single-Ended Outputs Only) The sysIO buffer pairs in the top banks of the device consist of two single-ended output drivers and two sets of single-ended input buffers (both ratioed and referenced). One of the referenced input buffers can also be configured as a differential input. The two pads in the pair are described as "true" and "comp", where the true pad is associated with the positive side of the differential input buffer and the comp (complementary) pad is associated with the negative side of the differential input buffer. Only the I/Os on the top and bottom banks have programmable PCI clamps. 2. Left and Right (Banks 2, 3, 6 and 7) sysIO Buffer Pairs (50% Differential and 100% Single-Ended Outputs) The sysIO buffer pairs in the left and right banks of the device consist of two single-ended output drivers, two sets of single-ended input buffers (both ratioed and referenced) and one differential output driver. One of the referenced input buffers can also be configured as a differential input. The two pads in the pair are described as "true" and "comp", where the true pad is associated with the positive side of the differential I/O, and the comp pad is associated with the negative side of the differential I/O. LVDS differential output drivers are available on 50% of the buffer pairs on the left and right banks. Typical sysIO I/O Behavior During Power-up The internal power-on-reset (POR) signal is deactivated when VCC and VCCAUX have reached satisfactory levels. After the POR signal is deactivated, the FPGA core logic becomes active. It is the user's responsibility to ensure that all other VCCIO banks are active with valid input logic levels to properly control the output logic states of all the I/O banks that are critical to the application. For more information on controlling the output logic state with valid input logic levels during power-up in LatticeXP2 devices, please see TN1136, LatticeXP2 sysIO Usage Guide. The VCC and VCCAUX supply the power to the FPGA core fabric, whereas the VCCIO supplies power to the I/O buffers. In order to simplify system design while providing consistent and predictable I/O behavior, it is recommended that the I/O buffers be powered-up prior to the FPGA core fabric. VCCIO supplies should be powered-up before or together with the VCC and VCCAUX supplies. Supported sysIO Standards The LatticeXP2 sysIO buffer supports both single-ended and differential standards. Single-ended standards can be further subdivided into LVCMOS, LVTTL and other standards. The buffers support the LVTTL, LVCMOS 1.2V, 1.5V, 1.8V, 2.5V and 3.3V standards. In the LVCMOS and LVTTL modes, the buffer has individual configuration options for drive strength, bus maintenance (weak pull-up, weak pull-down, or a bus-keeper latch) and open drain. Other single-ended standards supported include SSTL and HSTL. Differential standards supported include LVDS, MLVDS, BLVDS, LVPECL, RSDS, differential SSTL and differential HSTL. Tables 2-13 and 2-14 show the I/O standards (together with their supply and reference voltages) supported by LatticeXP2 devices. For further information on utilizing the sysIO buffer to support a variety of standards please see TN1136, LatticeXP2 sysIO Usage Guide. 2-35 Lattice Semiconductor Table 2-12. Supported Input Standards Input Standard Single Ended Interfaces LVTTL LVCMOS33 LVCMOS25 LVCMOS18 LVCMOS15 LVCMOS12 PCI33 HSTL18 Class I, II HSTL15 Class I SSTL33 Class I, II SSTL25 Class I, II SSTL18 Class I, II Differential Interfaces Differential SSTL18 Class I, II Differential SSTL25 Class I, II Differential SSTL33 Class I, II Differential HSTL15 Class I Differential HSTL18 Class I, II LVDS, MLVDS, LVPECL, BLVDS, RSDS -- -- -- -- -- -- -- -- -- -- -- -- -- 0.9 0.75 1.5 1.25 0.9 VREF (Nom.) Architecture LatticeXP2 Family Data Sheet VCCIO1 (Nom.) -- -- -- 1.8 1.5 -- -- -- -- -- -- -- -- -- -- -- -- -- 1. When not specified, VCCIO can be set anywhere in the valid operating range (page 3-1). 2-36 Lattice Semiconductor Table 2-13. Supported Output Standards Output Standard Single-ended Interfaces LVTTL LVCMOS33 LVCMOS25 LVCMOS18 LVCMOS15 LVCMOS12 LVCMOS33, Open Drain LVCMOS25, Open Drain LVCMOS18, Open Drain LVCMOS15, Open Drain LVCMOS12, Open Drain PCI33 HSTL18 Class I, II HSTL15 Class I SSTL33 Class I, II SSTL25 Class I, II SSTL18 Class I, II Differential Interfaces Differential SSTL33, Class I, II Differential SSTL25, Class I, II Differential SSTL18, Class I, II Differential HSTL18, Class I, II Differential HSTL15, Class I LVDS1, 2 MLVDS1 BLVDS1 LVPECL1 RSDS 1 Architecture LatticeXP2 Family Data Sheet Drive 4mA, 8mA, 12mA, 16mA, 20mA 4mA, 8mA, 12mA 16mA, 20mA 4mA, 8mA, 12mA, 16mA, 20mA 4mA, 8mA, 12mA, 16mA 4mA, 8mA 2mA, 6mA 4mA, 8mA, 12mA 16mA, 20mA 4mA, 8mA, 12mA 16mA, 20mA 4mA, 8mA, 12mA 16mA 4mA, 8mA 2mA, 6mA N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A 4mA, 8mA, 12mA, 16mA, 20mA VCCIO (Nom.) 3.3 3.3 2.5 1.8 1.5 1.2 -- -- -- -- -- 3.3 1.8 1.5 3.3 2.5 1.8 3.3 2.5 1.8 1.8 1.5 2.5 2.5 2.5 3.3 2.5 3.3 LVCMOS33D1 1. Emulated with external resistors. For more detail, please see TN1138, LatticeXP2 High Speed I/O Interface. 2. On the left and right edges, LVDS outputs are supported with a dedicated differential output driver on 50% of the I/Os. This solution does not require external resistors at the driver. Hot Socketing LatticeXP2 devices have been carefully designed to ensure predictable behavior during power-up and powerdown. Power supplies can be sequenced in any order. During power-up and power-down sequences, the I/Os remain in tri-state until the power supply voltage is high enough to ensure reliable operation. In addition, leakage into I/O pins is controlled to within specified limits. This allows for easy integration with the rest of the system. These capabilities make the LatticeXP2 ideal for many multiple power supply and hot-swap applications. IEEE 1149.1-Compliant Boundary Scan Testability All LatticeXP2 devices have boundary scan cells that are accessed through an IEEE 1149.1 compliant Test Access Port (TAP). This allows functional testing of the circuit board, on which the device is mounted, through a serial scan path that can access all critical logic nodes. Internal registers are linked internally, allowing test data to be shifted in 2-37 Lattice Semiconductor Architecture LatticeXP2 Family Data Sheet and loaded directly onto test nodes, or test data to be captured and shifted out for verification. The test access port consists of dedicated I/Os: TDI, TDO, TCK and TMS. The test access port has its own supply voltage VCCJ and can operate with LVCMOS3.3, 2.5, 1.8, 1.5 and 1.2 standards. For more information, please see TN1141, LatticeXP2 sysCONFIG Usage Guide. flexiFLASH Device Configuration The LatticeXP2 devices combine Flash and SRAM on a single chip to provide users with flexibility in device programming and configuration. Figure 2-33 provides an overview of the arrangement of Flash and SRAM configuration cells within the device. The remainder of this section provides an overview of these capabilities. See TN1141, LatticeXP2 sysCONFIG Usage Guide, for a more detailed description. Figure 2-33. Overview of Flash and SRAM Configuration Cells Within LatticeXP2 Devices EBR Blocks Flash Memory Massively Parallel Data Transfer Instant-ON Flash for Single-Chip Solution SRAM Configuration Bits EBR Blocks FlashBAK for EBR Storage Decryption and Device Lock TAG Memory Device Lock for Design Security SPI and JTAG At power-up, or on user command, data is transferred from the on-chip Flash memory to the SRAM configuration cells that control the operation of the device. This is done with massively parallel buses enabling the parts to operate within microseconds of the power supplies reaching valid levels; this capability is referred to as Instant-On. The on-chip Flash enables a single-chip solution eliminating the need for external boot memory. This Flash can be programmed through either the JTAG or Slave SPI ports of the device. The SRAM configuration space can also be infinitely reconfigured through the JTAG and Master SPI ports. The JTAG port is IEEE 1149.1 and IEEE 1532 compliant. As described in the EBR section of the data sheet, the FlashBAK capability of the parts enables the contents of the EBR blocks to be written back into the Flash storage area without erasing or reprogramming other aspects of the device configuration. Serial TAG memory is also available to allow the storage of small amounts of data such as calibration coefficients and error codes. For applications where security is important, the lack of an external bitstream provides a solution that is inherently more secure than SRAM only FPGAs. This is further enhanced by device locking. The device can be in one of three modes: 2-38 Lattice Semiconductor 1. Unlocked Architecture LatticeXP2 Family Data Sheet 2. Key Locked - Presenting the key through the programming interface allows the device to be unlocked. 3. Permanently Locked - The device is permanently locked. To further complement the security of the device a One Time Programmable (OTP) mode is available. Once the device is set in this mode it is not possible to erase or re-program the Flash portion of the device. Serial TAG Memory LatticeXP2 devices offer 0.6 to 3.3kbits of Flash memory in the form of Serial TAG memory. The TAG memory is an area of the on-chip Flash that can be used for non-volatile storage including electronic ID codes, version codes, date stamps, asset IDs and calibration settings. A block diagram of the TAG memory is shown in Figure 2-34. The TAG memory is accessed in the same way as external SPI Flash and it can be read or programmed either through JTAG, an external Slave SPI Port, or directly from FPGA logic. To read the TAG memory, a start address is specified and the entire TAG memory contents are read sequentially in a first-in-first-out manner. The TAG memory is independent of the Flash used for device configuration and given its use for general-purpose storage functions is always accessible regardless of the device security settings. For more information, see TN1137, LatticeXP2 Memory Usage Guide, and TN1141, LatticeXP2 sysCONFIG Usage Guide. Figure 2-34. Serial TAG Memory Diagram External Slave SPI Port JTAG FPGA Logic TDI Data Shift Register TDO External Slave SPI Port JTAG FPGA Logic Sequential Address Counter Flash Flash Memory Array Live Update Technology Many applications require field updates of the FPGA. LatticeXP2 devices provide three features that enable this configuration to be done in a secure and failsafe manner while minimizing impact on system operation. 1. Decryption Support LatticeXP2 devices provide on-chip, non-volatile key storage to support decryption of a 128-bit AES encrypted bitstream, securing designs and deterring design piracy. 2. TransFR (Transparent Field Reconfiguration) TransFR I/O (TFR) is a unique Lattice technology that allows users to update their logic in the field without interrupting system operation using a single ispVM command. TransFR I/O allows I/O states to be frozen during device configuration. This allows the device to be field updated with a minimum of system disruption and downtime. For more information please see TN1143, LatticeXP2 TransFR I/O. 3. Dual Boot Image Support Dual boot images are supported for applications requiring reliable remote updates of configuration data for the system FPGA. After the system is running with a basic configuration, a new boot image can be downloaded remotely and stored in a separate location in the configuration storage device. Any time after the update the LatticeXP2 can be re-booted from this new configuration file. If there is a problem such as corrupt data during download or incorrect version number with this new boot image, the LatticeXP2 device can revert back to the 2-39 Lattice Semiconductor Architecture LatticeXP2 Family Data Sheet original backup configuration and try again. This all can be done without power cycling the system. For more information please see TN1144, LatticeXP2 Dual Boot Usage Guide. For more information on device configuration, please see TN1141, LatticeXP2 sysCONFIG Usage Guide. Soft Error Detect (SED) Support LatticeXP2 devices have dedicated logic to perform Cyclic Redundancy Code (CRC) checks. During configuration, the configuration data bitstream can be checked with the CRC logic block. In addition, LatticeXP2 devices can be programmed for checking soft errors in SRAM. The SED operation can run in the background during user mode (normal operation). In the event a soft error occurs, the device can be programmed to either reload from a known good boot image (from internal Flash or external SPI memory) or generate an error signal. For further information on SED support, please see TN1130, LatticeXP2 Soft Error Detection (SED) Usage Guide. On-Chip Oscillator Every LatticeXP2 device has an internal CMOS oscillator that is used to derive a Master Clock (CCLK) for configuration. The oscillator and CCLK run continuously and are available to user logic after configuration is complete. The available CCLK frequencies are listed in Table 2-14. When a different CCLK frequency is selected during the design process, the following sequence takes place: 1. Device powers up with the default CCLK frequency. 2. During configuration, users select a different CCLK frequency. 3. CCLK frequency changes to the selected frequency after clock configuration bits are received. This internal CMOS oscillator is available to the user by routing it as an input clock to the clock tree. For further information on the use of this oscillator for configuration or user mode, please see TN1141, LatticeXP2 sysCONFIG Usage Guide. Table 2-14. Selectable CCLKs and Oscillator Frequencies During Configuration and User Mode CCLK/Oscillator (MHz) 2.51 3.12 4.3 5.4 6.9 8.1 9.2 10 13 15 20 26 32 40 54 803 1633 1. Software default oscillator frequency. 2. Software default CCLK frequency. 3. Frequency not valid for CCLK. 2-40 Lattice Semiconductor Architecture LatticeXP2 Family Data Sheet Density Shifting The LatticeXP2 family is designed to ensure that different density devices in the same family and in the same package have the same pinout. Furthermore, the architecture ensures a high success rate when performing design migration from lower density devices to higher density devices. In many cases, it is also possible to shift a lower utilization design targeted for a high-density device to a lower density device. However, the exact details of the final resource utilization will impact the likely success in each case. 2-41 LatticeXP2 Family Data Sheet DC and Switching Characteristics August 2008 Data Sheet DS1009 Absolute Maximum Ratings1, 2, 3 Supply Voltage VCC . . . . . . . . . . . . . . . . . . . -0.5 to 1.32V Supply Voltage VCCAUX . . . . . . . . . . . . . . . . -0.5 to 3.75V Supply Voltage VCCJ . . . . . . . . . . . . . . . . . . -0.5 to 3.75V Supply Voltage VCCPLL4 . . . . . . . . . . . . . . . . -0.5 to 3.75V Output Supply Voltage VCCIO . . . . . . . . . . . -0.5 to 3.75V Input or I/O Tristate Voltage Applied5 . . . . . . -0.5 to 3.75V Storage Temperature (Ambient) . . . . . . . . . -65 to 150C Junction Temperature Under Bias (Tj) . . . . . . . . . +125C 1. Stress above those listed under the "Absolute Maximum Ratings" may cause permanent damage to the device. Functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. 2. Compliance with the Lattice Thermal Management document is required. 3. All voltages referenced to GND. 4. VCCPLL only available on csBGA, PQFP and TQFP packages. 5. Overshoot and undershoot of -2V to (VIHMAX + 2) volts is permitted for a duration of <20ns. Recommended Operating Conditions Symbol VCC VCCAUX 4 Parameter Core Supply Voltage Auxiliary Supply Voltage PLL Supply Voltage I/O Driver Supply Voltage Supply Voltage for IEEE 1149.1 Test Access Port Junction Temperature, Commercial Operation Junction Temperature, Industrial Operation Min. 1.14 3.135 3.135 1.14 1.14 0 -40 Max. 1.26 3.465 3.465 3.465 3.465 85 100 Units V V V V V C C VCCPLL1 VCCIO2, 3, 4 VCCJ2 tJCOM tJIND 1. VCCPLL only available on csBGA, PQFP and TQFP packages. 2. If VCCIO or VCCJ is set to 1.2V, they must be connected to the same power supply as VCC. If VCCIO or VCCJ is set to 3.3V, they must be connected to the same power supply as VCCAUX. 3. See recommended voltages by I/O standard in subsequent table. 4. To ensure proper I/O behavior, VCCIO must be turned off at the same time or earlier than VCCAUX. On-Chip Flash Memory Specifications Symbol NPROGCYC tRETENTION Parameter Flash Programming Cycles per tRETENTION Flash Functional Programming Cycles Data Retention Max. 10,000 100,000 20 Units Cycles Years (c) 2008 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. www.latticesemi.com 3-1 DS1009 DC and Switching_01.6 Lattice Semiconductor DC and Switching Characteristics LatticeXP2 Family Data Sheet Hot Socketing Specifications1, 2, 3, 4 Symbol IDK 1. 2. 3. 4. Parameter Input or I/O Leakage Current Condition 0 VIN VIH (MAX.) Min. -- Typ. -- Max. +/-1 Units mA Insensitive to sequence of VCC, VCCAUX and VCCIO. However, assumes monotonic rise/fall rates for VCC, VCCAUX and VCCIO. 0 VCC VCC (MAX), 0 VCCIO VCCIO (MAX) or 0 VCCAUX VCCAUX (MAX). IDK is additive to IPU, IPW or IBH. LVCMOS and LVTTL only. DC Electrical Characteristics Over Recommended Operating Conditions Symbol IIL, IIH1 IPU IPD IBHLS IBHHS IBHLO IBHHO VBHT C1 C2 Parameter Input or I/O Low Leakage I/O Active Pull-up Current I/O Active Pull-down Current Condition 0 VIN VCCIO VCCIO VIN VIH (MAX) 0 VIN 0.7 VCCIO VIL (MAX) VIN VCCIO Min. -- -- -30 30 30 -30 -- -- VIL (MAX) VCCIO = 3.3V, 2.5V, 1.8V, 1.5V, 1.2V, VCC = 1.2V, VIO = 0 to VIH (MAX) VCCIO = 3.3V, 2.5V, 1.8V, 1.5V, 1.2V, VCC = 1.2V, VIO = 0 to VIH (MAX) -- -- Typ. -- -- -- -- -- -- -- -- -- 8 6 Max. 10 150 -150 210 -- -- 210 -150 VIH (MIN) -- -- Units A A A A A A A A V pf pf Bus Hold Low Sustaining Current VIN = VIL (MAX) Bus Hold High Sustaining Current VIN = 0.7 VCCIO Bus Hold Low Overdrive Current 0 VIN VCCIO Bus Hold High Overdrive Current 0 VIN VCCIO Bus Hold Trip Points I/O Capacitance2 Dedicated Input Capacitance 1. Input or I/O leakage current is measured with the pin configured as an input or as an I/O with the output driver tri-stated. It is not measured with the output driver active. Bus maintenance circuits are disabled. 2. TA 25oC, f = 1.0MHz. 3-2 Lattice Semiconductor DC and Switching Characteristics LatticeXP2 Family Data Sheet Supply Current (Standby)1, 2, 3, 4 Over Recommended Operating Conditions Symbol Parameter XP2-5 XP2-8 ICC Core Power Supply Current XP2-17 XP2-30 XP2-40 XP2-5 XP2-8 ICCAUX Auxiliary Power Supply Current6 XP2-17 XP2-30 XP2-40 ICCPLL ICCIO ICCJ 1. 2. 3. 4. 5. 6. Device Typical5 14 18 24 35 45 15 15 15 16 16 0.1 2 0.25 Units mA mA mA mA mA mA mA mA mA mA mA mA mA PLL Power Supply Current (per PLL) Bank Power Supply Current (per bank) VCCJ Power Supply Current For further information on supply current, please see TN1139, Power Estimation and Management for LatticeXP2 Devices. Assumes all outputs are tristated, all inputs are configured as LVCMOS and held at the VCCIO or GND. Frequency 0MHz. Pattern represents a "blank" configuration data file. TJ = 25oC, power supplies at nominal voltage. In fpBGA and ftBGA packages the PLLs are connected to and powered from the auxiliary power supply. For these packages, the actual auxiliary supply current is the sum of ICCAUX and ICCPLL. For csBGA, PQFP and TQFP packages the PLLs are powered independent of the auxiliary power supply. 3-3 Lattice Semiconductor DC and Switching Characteristics LatticeXP2 Family Data Sheet Initialization Supply Current1, 2, 3, 4, 5 Over Recommended Operating Conditions Symbol Parameter Device XP2-5 XP2-8 ICC Core Power Supply Current XP2-17 XP2-30 XP2-40 XP2-5 XP2-8 ICCAUX Auxiliary Power Supply Current7 XP2-17 XP2-30 XP2-40 ICCPLL ICCIO ICCJ 1. 2. 3. 4. 5. Typical (25C, Max. Supply)6 20 21 44 58 62 67 74 112 124 130 1.8 6.4 1.2 Units mA mA mA mA mA mA mA mA mA mA mA mA mA PLL Power Supply Current (per PLL) Bank Power Supply Current (per Bank) VCCJ Power Supply Current For further information on supply current, please see TN1139, Power Estimation and Management for LatticeXP2 Devices. Assumes all outputs are tristated, all inputs are configured as LVCMOS and held at the VCCIO or GND. Frequency 0MHz. Does not include additional current from bypass or decoupling capacitor across the supply. A specific configuration pattern is used that scales with the size of the device; consists of 75% PFU utilization, 50% EBR, and 25% I/O configuration. 6. TJ = 25C, power supplies at nominal voltage. 7. In fpBGA and ftBGA packages the PLLs are connected to and powered from the auxiliary power supply. For these packages, the actual auxiliary supply current is the sum of ICCAUX and ICCPLL. For csBGA, PQFP and TQFP packages the PLLs are powered independent of the auxiliary power supply. 3-4 Lattice Semiconductor DC and Switching Characteristics LatticeXP2 Family Data Sheet Programming and Erase Flash Supply Current1, 2, 3, 4, 5 Over Recommended Operating Conditions Symbol Parameter XP2-5 XP2-8 ICC Core Power Supply Current XP2-17 XP2-30 XP2-40 XP2-5 XP2-8 ICCAUX Auxiliary Power Supply Current7 XP2-17 XP2-30 XP2-40 ICCPLL ICCIO ICCJ 1. 2. 3. 4. 5. 6. 7. Device Typical (25C, Max. Supply)6 17 21 28 36 50 64 66 83 87 88 0.1 5 14 Units mA mA mA mA mA mA mA mA mA mA mA mA mA PLL Power Supply Current (per PLL) Bank Power Supply Current (per Bank) VCCJ Power Supply Current8 8. For further information on supply current, please see TN1139, Power Estimation and Management for LatticeXP2 Devices. Assumes all outputs are tristated, all inputs are configured as LVCMOS and held at the VCCIO or GND. Frequency 0MHz (excludes dynamic power from FPGA operation). A specific configuration pattern is used that scales with the size of the device; consists of 75% PFU utilization, 50% EBR, and 25% I/O configuration. Bypass or decoupling capacitor across the supply. TJ = 25C, power supplies at nominal voltage. In fpBGA and ftBGA packages the PLLs are connected to and powered from the auxiliary power supply. For these packages, the actual auxiliary supply current is the sum of ICCAUX and ICCPLL. For csBGA, PQFP and TQFP packages the PLLs are powered independent of the auxiliary power supply. When programming via JTAG. 3-5 Lattice Semiconductor DC and Switching Characteristics LatticeXP2 Family Data Sheet sysIO Recommended Operating Conditions Over Recommended Operating Conditions VCCIO Standard LVCMOS332 LVCMOS25 LVCMOS18 LVCMOS15 LVCMOS122 LVTTL332 PCI33 SSTL18_I , SSTL18_II2 SSTL25_I2, SSTL25_II2 SSTL33_I2, SSTL33_II2 HSTL15_I2 HSTL18_I2, HSTL18_II2 LVDS252 MLVDS25 BLVDS25 RSDS1, 2 SSTL18D_I , SSTL18D_II2 SSTL25D_ I2, SSTL25D_II2 SSTL33D_ I2, SSTL33D_ II2 HSTL15D_ I2 HSTL18D_ I2, HSTL18D_ II2 2 1 2 2 VREF (V) Max. 3.465 2.625 1.89 1.575 1.26 3.465 3.465 1.89 2.625 3.465 1.575 1.89 2.625 2.625 3.465 2.625 2.625 1.89 2.625 3.465 1.575 1.89 Min. -- -- -- -- -- -- -- 0.833 1.15 1.3 0.68 0.816 -- -- -- -- -- -- -- -- -- -- Typ. -- -- -- -- -- -- -- 0.9 1.25 1.5 0.75 0.9 -- -- -- -- -- -- -- -- -- -- Max. -- -- -- -- -- -- -- 0.969 1.35 1.7 0.9 1.08 -- -- -- -- -- -- -- -- -- -- Min. 3.135 2.375 1.71 1.425 1.14 3.135 3.135 1.71 2.375 3.135 1.425 1.71 2.375 2.375 3.135 2.375 2.375 1.71 2.375 3.135 1.425 1.71 Typ. 3.3 2.5 1.8 1.5 1.2 3.3 3.3 1.8 2.5 3.3 1.5 1.8 2.5 2.5 3.3 2.5 2.5 1.8 2.5 3.3 1.5 1.8 LVPECL331, 2 1, 2 1. Inputs on chip. Outputs are implemented with the addition of external resistors. 2. Input on this standard does not depend on the value of VCCIO. 3-6 Lattice Semiconductor DC and Switching Characteristics LatticeXP2 Family Data Sheet sysIO Single-Ended DC Electrical Characteristics Over Recommended Operating Conditions Input/Output Standard LVCMOS33 VIL Min. (V) -0.3 Max. (V) 0.8 Min. (V) 2.0 VIH Max. (V) 3.6 VOL Max. (V) 0.4 0.2 LVTTL33 -0.3 0.8 2.0 3.6 0.4 0.2 LVCMOS25 -0.3 0.7 1.7 3.6 0.4 0.2 LVCMOS18 -0.3 0.35 VCCIO 0.65 VCCIO 3.6 0.4 0.2 LVCMOS15 LVCMOS12 PCI33 SSTL33_I SSTL33_II SSTL25_I SSTL25_II SSTL18_I SSTL18_II HSTL15_I HSTL18_I HSTL18_II -0.3 -0.3 -0.3 -0.3 -0.3 -0.3 -0.3 -0.3 -0.3 -0.3 -0.3 -0.3 0.35 VCCIO 0.35 VCC 0.3 VCCIO VREF - 0.2 VREF - 0.2 VREF - 0.18 VREF - 0.18 0.65 VCCIO 0.65 VCC 0.5 VCCIO VREF + 0.2 VREF + 0.2 VREF + 0.18 VREF + 0.18 3.6 3.6 3.6 3.6 3.6 3.6 3.6 3.6 3.6 3.6 3.6 3.6 0.4 0.2 0.4 0.2 VOH Min. (V) VCCIO - 0.4 VCCIO - 0.2 VCCIO - 0.4 VCCIO - 0.2 VCCIO - 0.4 VCCIO - 0.2 VCCIO - 0.4 VCCIO - 0.2 VCCIO - 0.4 VCCIO - 0.2 VCCIO - 0.4 VCCIO - 0.2 IOL1 (mA) 20, 16, 12, 8, 4 0.1 20, 16, 12, 8, 4 0.1 20, 16, 12, 8, 4 0.1 16, 12, 8, 4 0.1 8, 4 0.1 6, 2 0.1 1.5 8 16 7.6 12 15.2 20 6.7 8 11 4 8 8 12 16 IOH1 (mA) -20, -16, -12, -8, -4 -0.1 -20, -16, -12, -8, -4 -0.1 -20, -16, -12, -8, -4 -0.1 -16, -12, -8, -4 -0.1 -8, -4 -0.1 -6, -2 -0.1 -0.5 -8 -16 -7.6 -12 -15.2 -20 -6.7 -8 -11 -4 -8 -8 -12 -16 0.1 VCCIO 0.9 VCCIO 0.7 VCCIO - 1.1 0.5 0.54 0.35 0.4 0.28 0.4 0.4 0.4 VCCIO - 0.9 VCCIO - 0.62 VCCIO - 0.43 VCCIO - 0.4 VCCIO - 0.28 VCCIO - 0.4 VCCIO - 0.4 VCCIO - 0.4 VREF - 0.125 VREF + 0.125 VREF - 0.125 VREF + 0.125 VREF - 0.1 VREF - 0.1 VREF - 0.1 VREF + 0.1 VREF + 0.1 VREF + 0.1 1. The average DC current drawn by I/Os between GND connections, or between the last GND in an I/O bank and the end of an I/O bank, as shown in the logic signal connections table shall not exceed n * 8mA, where n is the number of I/Os between bank GND connections or between the last GND in a bank and the end of a bank. 3-7 Lattice Semiconductor DC and Switching Characteristics LatticeXP2 Family Data Sheet sysIO Differential Electrical Characteristics LVDS Over Recommended Operating Conditions Parameter VINP, VINM VCM VTHD IIN VOH VOL VOD VOD VOS VOS ISA,ISA ISAB Description Input Voltage Input Common Mode Voltage Differential Input Threshold Input Current Output High Voltage for VOP or VOM Output Low Voltage for VOP or VOM Output Voltage Differential Change in VOD Between High and Low Output Voltage Offset Change in VOS Between H and L Output Short Circuit Current Output Short Circuit Current VOD = 0V Driver Outputs Shorted to Ground VOD = 0V Driver Outputs Shorted to Each Other (VOP + VOM)/2, RT = 100 Ohm Half the Sum of the Two Inputs Difference Between the Two Inputs Power On or Power Off RT = 100 Ohm RT = 100 Ohm (VOP - VOM), RT = 100 Ohm Test Conditions Min. 0 0.05 +/-100 -- -- 0.9V 250 -- 1.125 -- -- -- Typ. -- -- -- -- 1.38 1.03 350 -- 1.20 -- -- -- Max. 2.4 2.35 -- +/-10 1.60 -- 450 50 1.375 50 24 12 Units V V mV A V V mV mV V mV mA mA Differential HSTL and SSTL Differential HSTL and SSTL outputs are implemented as a pair of complementary single-ended outputs. All allowable single-ended output classes (class I and class II) are supported in this mode. For further information on LVPECL, RSDS, MLVDS, BLVDS and other differential interfaces please see details of additional technical information at the end of this data sheet. LVDS25E The top and bottom sides of LatticeXP2 devices support LVDS outputs via emulated complementary LVCMOS outputs in conjunction with a parallel resistor across the driver outputs. The scheme shown in Figure 3-1 is one possible solution for point-to-point signals. Figure 3-1. LVDS25E Output Termination Example VCCIO = 2.5V (5%) RS=158 ohms (1%) 8 mA VCCIO = 2.5V (5%) RS=158 ohms (1%) 8 mA RP = 140 ohms (1%) RT = 100 ohms (1%) + - Transmission line, Zo = 100 ohm differential ON-chip OFF-chip OFF-chip ON-chip 3-8 Lattice Semiconductor Table 3-1. LVDS25E DC Conditions Parameter VCCIO ZOUT RS RP RT VOH VOL VOD VCM ZBACK IDC Description Output Driver Supply (+/-5%) Driver Impedance Driver Series Resistor (+/-1%) Driver Parallel Resistor (+/-1%) Receiver Termination (+/-1%) Output High Voltage (after R1) Output Low Voltage (after R1) Output Differential Voltage (After R1) Output Common Mode Voltage Back Impedance DC Output Current DC and Switching Characteristics LatticeXP2 Family Data Sheet Typical 2.50 20 158 140 100 1.43 1.07 0.35 1.25 100.5 6.03 Units V V V V V mA LVCMOS33D All I/O banks support emulated differential I/O using the LVCMOS33D I/O type. This option, along with the external resistor network, provides the system designer the flexibility to place differential outputs on an I/O bank with 3.3V VCCIO. The default drive current for LVCMOS33D output is 12mA with the option to change the device strength to 4mA, 8mA, 16mA or 20mA. Follow the LVCMOS33 specifications for the DC characteristics of the LVCMOS33D. 3-9 Lattice Semiconductor BLVDS DC and Switching Characteristics LatticeXP2 Family Data Sheet The LatticeXP2 devices support the BLVDS standard. This standard is emulated using complementary LVCMOS outputs in conjunction with a parallel external resistor across the driver outputs. BLVDS is intended for use when multi-drop and bi-directional multi-point differential signaling is required. The scheme shown in Figure 3-2 is one possible solution for bi-directional multi-point differential signals. Figure 3-2. BLVDS Multi-point Output Example Heavily loaded backplane, effective Zo ~ 45 to 90 ohms differential 2.5V 16mA RS = 90 ohms RS = 90 ohms 2.5V 16mA 45-90 ohms 2.5V 16mA RTL 45-90 ohms RTR 2.5V 16mA RS = 90 ohms RS = 90 ohms + - RS = 90 ohms ... + RS = 90 ohms RS = 90 ohms RS = 90 ohms + - 2.5V 16mA 2.5V 16mA 2.5V 16mA 2.5V 16mA - Table 3-2. BLVDS DC Conditions1 Over Recommended Operating Conditions Typical Parameter VCCIO ZOUT RS RTLEFT RTRIGHT VOH VOL VOD VCM IDC Description Output Driver Supply (+/- 5%) Driver Impedance Driver Series Resistor (+/- 1%) Driver Parallel Resistor (+/- 1%) Receiver Termination (+/- 1%) Output High Voltage (After R1) Output Low Voltage (After R1) Output Differential Voltage (After R1) Output Common Mode Voltage DC Output Current Zo = 45 2.50 10.00 90.00 45.00 45.00 1.38 1.12 0.25 1.25 11.24 Zo = 45 2.50 10.00 90.00 90.00 90.00 1.48 1.02 0.46 1.25 10.20 Units V V V V V mA 1. For input buffer, see LVDS table. 3-10 + Lattice Semiconductor LVPECL DC and Switching Characteristics LatticeXP2 Family Data Sheet The LatticeXP2 devices support the differential LVPECL standard. This standard is emulated using complementary LVCMOS outputs in conjunction with a parallel resistor across the driver outputs. The LVPECL input standard is supported by the LVDS differential input buffer. The scheme shown in Figure 3-3 is one possible solution for pointto-point signals. Figure 3-3. Differential LVPECL VCCIO = 3.3V (+/-5%) 16mA VCCIO = 3.3V (+/-5%) 16mA On-chip Off-chip + - RS = 93.1 ohms (+/-1%) RS = 93.1 ohms (+/-1%) RP = 196 ohms (+/-1%) RT = 100 ohms (+/-1%) Transmission line, Zo = 100 ohm differential Off-chip On-chip Table 3-3. LVPECL DC Conditions1 Over Recommended Operating Conditions Parameter VCCIO ZOUT RS RP RT VOH VOL VOD VCM ZBACK IDC Description Output Driver Supply (+/-5%) Driver Impedance Driver Series Resistor (+/-1%) Driver Parallel Resistor (+/-1%) Receiver Termination (+/-1%) Output High Voltage (After R1) Output Low Voltage (After R1) Output Differential Voltage (After R1) Output Common Mode Voltage Back Impedance DC Output Current Typical 3.30 10 93 196 100 2.05 1.25 0.80 1.65 100.5 12.11 Units V V V V V mA 1. For input buffer, see LVDS table. 3-11 Lattice Semiconductor RSDS DC and Switching Characteristics LatticeXP2 Family Data Sheet The LatticeXP2 devices support differential RSDS standard. This standard is emulated using complementary LVCMOS outputs in conjunction with a parallel resistor across the driver outputs. The RSDS input standard is supported by the LVDS differential input buffer. The scheme shown in Figure 3-4 is one possible solution for RSDS standard implementation. Resistor values in Figure 3-4 are industry standard values for 1% resistors. Figure 3-4. RSDS (Reduced Swing Differential Standard) VCCIO = 2.5V (+/-5%) 8mA VCCIO = 2.5V (+/-5%) 8mA On-chip Off-chip RP = 121 ohms (+/-1%) RT = 100 ohms (+/-1%) + RS = 294 ohms (+/-1%) RS = 294 ohms (+/-1%) Transmission line, Zo = 100 ohm differential Off-chip On-chip Table 3-4. RSDS DC Conditions1 Over Recommended Operating Conditions Parameter VCCIO ZOUT RS RP RT VOH VOL VOD VCM ZBACK IDC Description Output Driver Supply (+/-5%) Driver Impedance Driver Series Resistor (+/-1%) Driver Parallel Resistor (+/-1%) Receiver Termination (+/-1%) Output High Voltage (After R1) Output Low Voltage (After R1) Output Differential Voltage (After R1) Output Common Mode Voltage Back Impedance DC Output Current Typical 2.50 20 294 121 100 1.35 1.15 0.20 1.25 101.5 3.66 Units V V V V V mA 1. For input buffer, see LVDS table. 3-12 Lattice Semiconductor MLVDS DC and Switching Characteristics LatticeXP2 Family Data Sheet The LatticeXP2 devices support the differential MLVDS standard. This standard is emulated using complementary LVCMOS outputs in conjunction with a parallel resistor across the driver outputs. The MLVDS input standard is supported by the LVDS differential input buffer. The scheme shown in Figure 3-5 is one possible solution for MLVDS standard implementation. Resistor values in Figure 3-5 are industry standard values for 1% resistors. Figure 3-5. MLVDS (Reduced Swing Differential Standard) Heavily loaded backplace, effective Zo~50 to 70 ohms differential 2.5V 16mA RTL 50 to 70 ohms +/-1% 50 to 70 ohms +/-1% RTR RS = 35ohms RS = 35ohms 2.5V 16mA 2.5V 16mA 2.5V 16mA RS = 35ohms + RS = 35ohms RS = 35ohms RS = 35ohms RS = 35ohms RS = 35ohms + - ... + + 2.5V 16mA 16mA 2.5V 16mA 2.5V 16mA 2.5V Table 3-5. MLVDS DC Conditions1 Typical Parameter VCCIO ZOUT RS RTLEFT RTRIGHT VOH VOL VOD VCM IDC Description Output Driver Supply (+/-5%) Driver Impedance Driver Series Resistor (+/-1%) Driver Parallel Resistor (+/-1%) Receiver Termination (+/-1%) Output High Voltage (After R1) Output Low Voltage (After R1) Output Differential Voltage (After R1) Output Common Mode Voltage DC Output Current Zo=50 2.50 10.00 35.00 50.00 50.00 1.52 0.98 0.54 1.25 21.74 Zo=70 2.50 10.00 35.00 70.00 70.00 1.60 0.90 0.70 1.25 20.00 Units V V V V V mA 1. For input buffer, see LVDS table. For further information on LVPECL, RSDS, MLVDS, BLVDS and other differential interfaces please see details of additional technical information at the end of this data sheet. - 3-13 - Lattice Semiconductor DC and Switching Characteristics LatticeXP2 Family Data Sheet Typical Building Block Function Performance1 Pin-to-Pin Performance (LVCMOS25 12mA Drive) Function Basic Functions 16-bit Decoder 32-bit Decoder 64-bit Decoder 4:1 MUX 8:1 MUX 16:1 MUX 32:1 MUX 4.4 5.2 5.6 3.7 3.9 4.3 4.5 ns ns ns ns ns ns ns -7 Timing Units Register-to-Register Performance Function Basic Functions 16-bit Decoder 32-bit Decoder 64-bit Decoder 4:1 MUX 8:1 MUX 16:1 MUX 32:1 MUX 8-bit Adder 16-bit Adder 64-bit Adder 16-bit Counter 32-bit Counter 64-bit Counter 64-bit Accumulator Embedded Memory Functions 512x36 Single Port RAM, EBR Output Registers 1024x18 True-Dual Port RAM (Write Through or Normal, EBR Output Registers) 1024x18 True-Dual Port RAM (Write Through or Normal, PLC Output Registers) Distributed Memory Functions 16x4 Pseudo-Dual Port RAM (One PFU) 32x2 Pseudo-Dual Port RAM 64x1 Pseudo-Dual Port RAM DSP Functions 18x18 Multiplier (All Registers) 9x9 Multiplier (All Registers) 36x36 Multiply (All Registers) 18x18 Multiply/Accumulate (Input and Output Registers) 18x18 Multiply-Add/Sub-Sum (All Registers) 342 342 330 218 292 MHz MHz MHz MHz MHz 760 455 351 MHz MHz MHz 315 315 231 MHz MHz MHz 521 537 484 744 678 616 529 570 507 293 541 440 321 261 MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz -7 Timing Units 3-14 Lattice Semiconductor Register-to-Register Performance (Continued) Function DSP IP Functions 16-Tap Fully-Parallel FIR Filter 1024-pt FFT 8X8 Matrix Multiplication DC and Switching Characteristics LatticeXP2 Family Data Sheet -7 Timing 198 221 196 Units MHz MHz MHz 1. These timing numbers were generated using the ispLEVER design tool. Exact performance may vary with device, design and tool version. The tool uses internal parameters that have been characterized but are not tested on every device. Timing v. A 0.12 Derating Timing Tables Logic timing provided in the following sections of this data sheet and the ispLEVER design tools are worst case numbers in the operating range. Actual delays at nominal temperature and voltage for best case process, can be much better than the values given in the tables. The ispLEVER design tool can provide logic timing numbers at a particular temperature and voltage. 3-15 Lattice Semiconductor DC and Switching Characteristics LatticeXP2 Family Data Sheet LatticeXP2 External Switching Characteristics Over Recommended Operating Conditions -7 Parameter Description Device XP2-5 XP2-8 tCO Clock to Output - PIO Output Register XP2-17 XP2-30 XP2-40 XP2-5 XP2-8 tSU Clock to Data Setup - PIO Input Register XP2-17 XP2-30 XP2-40 XP2-5 XP2-8 tH Clock to Data Hold - PIO Input Register XP2-17 XP2-30 XP2-40 XP2-5 XP2-8 tSU_DEL Clock to Data Setup - PIO Input Register with Data Input Delay XP2-17 XP2-30 XP2-40 XP2-5 XP2-8 tH_DEL Clock to Data Hold - PIO Input Register with Input Data Delay XP2-17 XP2-30 XP2-40 fMAX_IO Clock Frequency of I/O and PFU XP2 Register XP2-5 XP2-8 tCOE Clock to Output - PIO Output Register XP2-17 XP2-30 XP2-40 XP2-5 XP2-8 tSUE Clock to Data Setup - PIO Input Register XP2-17 XP2-30 XP2-40 Min. -- -- -- -- -- 0.00 0.00 0.00 0.00 0.00 1.40 1.40 1.40 1.40 1.40 1.40 1.40 1.40 1.40 1.40 0.00 0.00 0.00 0.00 0.00 -- Max. 3.80 3.80 3.80 4.00 4.00 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 420 Min. -- -- -- -- -- 0.00 0.00 0.00 0.00 0.00 1.70 1.70 1.70 1.70 1.70 1.70 1.70 1.70 1.70 1.70 0.00 0.00 0.00 0.00 0.00 -- General I/O Pin Parameters (using Primary Clock without PLL)1 4.20 4.20 4.20 4.40 4.40 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 357 -- -- -- -- -- 0.00 0.00 0.00 0.00 0.00 1.90 1.90 1.90 1.90 1.90 1.90 1.90 1.90 1.90 1.90 0.00 0.00 0.00 0.00 0.00 -- 4.60 4.60 4.60 4.90 4.90 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 311 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns MHz -6 Max. Min. -5 Max. Units General I/O Pin Parameters (using Edge Clock without PLL)1 -- -- -- -- -- 0.00 0.00 0.00 0.00 0.00 3.20 3.20 3.20 3.20 3.20 -- -- -- -- -- -- -- -- -- -- 0.00 0.00 0.00 0.00 0.00 3.60 3.60 3.60 3.60 3.60 -- -- -- -- -- -- -- -- -- -- 0.00 0.00 0.00 0.00 0.00 3.90 3.90 3.90 3.90 3.90 -- -- -- -- -- ns ns ns ns ns ns ns ns ns ns 3-16 Lattice Semiconductor DC and Switching Characteristics LatticeXP2 Family Data Sheet LatticeXP2 External Switching Characteristics (Continued) Over Recommended Operating Conditions -7 Parameter Description Device XP2-5 XP2-8 tHE Clock to Data Hold - PIO Input Register XP2-17 XP2-30 XP2-40 XP2-5 XP2-8 tSU_DELE Clock to Data Setup - PIO Input Register with Data Input Delay XP2-17 XP2-30 XP2-40 XP2-5 XP2-8 tH_DELE Clock to Data Hold - PIO Input Register with Input Data Delay XP2-17 XP2-30 XP2-40 fMAX_IOE Clock Frequency of I/O and PFU XP2 Register XP2-5 XP2-8 tCOPLL Clock to Output - PIO Output Register XP2-17 XP2-30 XP2-40 XP2-5 XP2-8 tSUPLL Clock to Data Setup - PIO Input Register XP2-17 XP2-30 XP2-40 XP2-5 XP2-8 tHPLL Clock to Data Hold - PIO Input Register XP2-17 XP2-30 XP2-40 XP2-5 XP2-8 tSU_DELPLL Clock to Data Setup - PIO Input Register with Data Input Delay XP2-17 XP2-30 XP2-40 Min. 1.00 1.00 1.00 1.20 1.20 1.00 1.00 1.00 1.20 1.20 0.00 0.00 0.00 0.00 0.00 -- Max. -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 420 Min. 1.30 1.30 1.30 1.60 1.60 1.30 1.30 1.30 1.60 1.60 0.00 0.00 0.00 0.00 0.00 -- -6 Max. -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 357 Min. 1.60 1.60 1.60 1.90 1.90 1.60 1.60 1.60 1.90 1.90 0.00 0.00 0.00 0.00 0.00 -- -5 Max. -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 311 Units ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns MHz General I/O Pin Parameters (using Primary Clock with PLL)1 -- -- -- -- -- 1.00 1.00 1.00 1.00 1.00 0.90 0.90 0.90 1.00 1.00 1.90 1.90 1.90 2.00 2.00 3.00 3.00 3.00 3.00 3.00 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 1.20 1.20 1.20 1.20 1.20 1.10 1.10 1.10 1.20 1.20 2.10 2.10 2.10 2.20 2.20 3.30 3.30 3.30 3.30 3.30 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 1.40 1.40 1.40 1.40 1.40 1.30 1.30 1.30 1.40 1.40 2.30 2.30 2.30 2.40 2.40 3.70 3.70 3.70 3.70 3.70 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 3-17 Lattice Semiconductor DC and Switching Characteristics LatticeXP2 Family Data Sheet LatticeXP2 External Switching Characteristics (Continued) Over Recommended Operating Conditions -7 Parameter Description Device XP2-5 XP2-8 tH_DELPLL Clock to Data Hold - PIO Input Register with Input Data Delay XP2-17 XP2-30 XP2-40 DDR2 and DDR23 I/O Pin Parameters tDVADQ tDVEDQ tDQVBS tDQVAS fMAX_DDR fMAX_DDR2 Primary Clock fMAX_PRI tW_PRI tSKEW_PRI Frequency for Primary Clock Tree XP2 Clock Pulse Width for Primary Clock Primary Clock Skew Within a Bank Frequency for Edge Clock Clock Pulse Width for Edge Clock XP2 XP2 -- 1 -- 420 -- 160 -- 1 -- 357 -- 160 -- 1 -- 311 -- 160 MHz ns ps Data Valid After DQS (DDR Read) Data Hold After DQS (DDR Read) Data Valid Before DQS Data Valid After DQS DDR Clock Frequency DDR Clock Frequency XP2 XP2 XP2 XP2 XP2 XP2 -- 0.71 0.25 0.25 95 133 0.29 -- -- -- 200 200 -- 0.71 0.25 0.25 95 133 0.29 -- -- -- 166 200 -- 0.71 0.25 0.25 95 133 0.29 -- -- -- 133 166 UI UI UI UI MHz MHz Min. 0.00 0.00 0.00 0.00 0.00 Max. -- -- -- -- -- Min. 0.00 0.00 0.00 0.00 0.00 -6 Max. -- -- -- -- -- Min. 0.00 0.00 0.00 0.00 0.00 -5 Max. -- -- -- -- -- Units ns ns ns ns ns Edge Clock (ECLK1 and ECLK2) fMAX_ECLK tW_ECLK tSKEW_ECLK XP2 XP2 -- 1 -- 420 -- 130 -- 1 -- 357 -- 130 -- 1 -- 311 -- 130 MHz ns ps Edge Clock Skew Within an Edge XP2 of the Device 1. General timing numbers based on LVCMOS 2.5, 12mA, 0pf load. 2. DDR timing numbers based on SSTL25. 3. DDR2 timing numbers based on SSTL18. Timing v. A 0.12 3-18 Lattice Semiconductor DC and Switching Characteristics LatticeXP2 Family Data Sheet LatticeXP2 Internal Switching Characteristics1 Over Recommended Operating Conditions -7 Parameter Description LUT4 delay (A to D inputs to F output) LUT6 delay (A to D inputs to OFX output) Set/Reset to output of PFU (Asynchronous) Clock to Mux (M0,M1) Input Setup Time Clock to Mux (M0,M1) Input Hold Time Clock to D input setup time Clock to D input hold time Clock to Q delay, (D-type Register Configuration) Asynchronous reset recovery time for PFU Logic Asynchronous reset time for PFU Logic Clock to Output (F Port) Data Setup Time Data Hold Time Address Setup Time Address Hold Time Write/Read Enable Setup Time Write/Read Enable Hold Time Input Buffer Delay (LVCMOS25) Output Buffer Delay (LVCMOS25) Input Register Setup Time (Data Before Clock) Input Register Hold Time (Data after Clock) Output Register Clock to Output Delay Input Register Clock Enable Setup Time Input Register Clock Enable Hold Time Set/Reset Setup Time Set/Reset Hold Time Asynchronous reset recovery time for IO Logic Min. Max. Min. PFU/PFF Logic Mode Timing tLUT4_PFU tLUT6_PFU tLSR_PFU tSUM_PFU tHM_PFU tSUD_PFU tHD_PFU tCK2Q_PFU tRSTREC_PFU tRST_PFU -- -- -- 0.154 -0.061 0.061 0.002 -- -- -- 0.216 0.304 0.720 -- -- -- -- 0.342 0.520 0.720 -- -- -- 0.151 -0.057 0.077 0.003 -- -- -- 0.238 0.399 0.769 -- -- -- -- 0.363 0.634 0.769 -- -- -- 0.148 -0.053 0.093 0.003 -- -- -- 0.260 0.494 0.818 -- -- -- -- 0.383 0.748 0.818 ns ns ns ns ns ns ns ns ns ns -6 Max. Min. -5 Max. Units PFU Dual Port Memory Mode Timing tCORAM_PFU tSUDATA_PFU tHDATA_PFU tSUADDR_PFU tHADDR_PFU tSUWREN_PFU tHWREN_PFU tIN_PIO tOUT_PIO -- -0.206 0.239 -0.294 0.295 -0.146 0.158 -- -- 1.082 -- -- -- -- -- -- 0.858 1.561 -- -0.240 0.275 -0.333 0.333 -0.169 0.182 -- -- 1.267 -- -- -- -- -- -- 0.766 1.403 -- -0.274 0.312 -0.371 0.371 -0.193 0.207 -- -- 1.452 -- -- -- -- -- -- 0.674 1.246 ns ns ns ns ns ns ns ns ns PIO Input/Output Buffer Timing IOLOGIC Input/Output Timing tSUI_PIO tHI_PIO tCOO_PIO tSUCE_PIO tHCE_PIO tSULSR_PIO tHLSR_PIO tRSTREC_PIO 0.583 0.062 -- 0.032 -0.022 0.184 -0.080 0.228 -- -- 0.608 -- -- -- -- -- 0.893 0.322 -- 0.037 -0.025 0.201 -0.086 0.247 -- -- 0.661 -- -- -- -- -- 1.201 0.482 -- 0.041 -0.028 0.217 -0.093 0.266 -- -- 0.715 -- -- -- -- -- ns ns ns ns ns ns ns ns 3-19 Lattice Semiconductor DC and Switching Characteristics LatticeXP2 Family Data Sheet LatticeXP2 Internal Switching Characteristics1 (Continued) Over Recommended Operating Conditions -7 Parameter tRST_PIO tDEL EBR Timing tCO_EBR tCOO_EBR tSUDATA_EBR tHDATA_EBR tSUADDR_EBR tHADDR_EBR tSUWREN_EBR tHWREN_EBR tSUCE_EBR tHCE_EBR tRSTO_EBR tSUBE_EBR tHBE_EBR tRSTREC_EBR tRST_EBR Clock (Read) to Output from Address or Data Clock (Write) to Output from EBR Output Register Setup Data to EBR Memory (Write Clk) Hold Data to EBR Memory (Write Clk) Setup Address to EBR Memory (Write Clk) Hold Address to EBR Memory (Write Clk) Setup Write/Read Enable to EBR Memory (Write/Read Clk) Hold Write/Read Enable to EBR Memory (Write/Read Clk) Clock Enable Setup Time to EBR Output Register (Read Clk) Clock Enable Hold Time to EBR Output Register (Read Clk) Reset To Output Delay Time from EBR Output Register (Asynchronous) Byte Enable Set-Up Time to EBR Output Register Byte Enable Hold Time to EBR Output Register Dynamic Delay on Each PIO Asynchronous reset recovery time for EBR Asynchronous reset time for EBR -- -- -0.167 0.194 -0.117 0.157 -0.135 0.158 0.144 -0.097 -- -0.117 0.157 0.233 -- 2.774 0.360 -- -- -- -- -- -- -- -- 1.156 -- -- -- 1.156 -- -- -0.198 0.231 -0.137 0.182 -0.159 0.186 0.160 -0.113 -- -0.137 0.182 0.291 -- 3.142 0.408 -- -- -- -- -- -- -- -- 1.341 -- -- -- 1.341 -- -- -0.229 0.267 -0.157 0.207 -0.182 0.214 0.176 -0.129 -- -0.157 0.207 0.347 -- 3.510 0.456 -- -- -- -- -- -- -- -- 1.526 -- -- -- 1.526 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Description Asynchronous reset time for PFU Logic Dynamic Delay Step Size Min. -- 0.035 Max. 0.386 0.035 Min. -- 0.035 -6 Max. 0.419 0.035 Min. -- 0.035 -5 Max. 0.452 0.035 Units ns ns PLL Parameters After RSTK De-assert, Recovery tRSTKREC_PLL Time Before Next Clock Edge Can Toggle K-divider Counter After RST De-assert, Recovery Time Before Next Clock Edge Can Toggle M-divider Counter (Applies to M-Divider Portion of RST Only2) Input Register Setup Time Input Register Hold Time Pipeline Register Setup Time 1.000 -- 1.000 -- 1.000 -- ns tRSTREC_PLL 1.000 -- 1.000 -- 1.000 -- ns DSP Block Timing tSUI_DSP tHI_DSP tSUP_DSP 0.135 0.021 2.505 -- -- -- 0.151 -0.006 2.784 -- -- -- 0.166 -0.031 3.064 -- -- -- ns ns ns 3-20 Lattice Semiconductor DC and Switching Characteristics LatticeXP2 Family Data Sheet LatticeXP2 Internal Switching Characteristics1 (Continued) Over Recommended Operating Conditions -7 Parameter tHP_DSP tSUO_DSP tHO_DSP tCOI_DSP 3 -6 Max. -- -- -- 4.513 2.153 0.569 -- -- Min. -0.890 5.413 -1.604 -- -- -- -0.298 0.338 Max. -- -- -- 4.947 2.272 0.600 -- -- Min. -0.994 5.931 -1.770 -- -- -- -0.327 0.371 -5 Max. -- -- -- 5.382 2.391 0.631 -- -- Units ns ns ns ns ns ns ns ns Description Pipeline Register Hold Time Output Register Setup Time Output Register Hold Time Input Register Clock to Output Time Pipeline Register Clock to Output Time Output Register Clock to Output Time AdSub Input Register Setup Time AdSub Input Register Hold Time Min. -0.787 4.896 -1.439 -- -- -- -0.270 0.306 tCOP_DSP3 tCOO_DSP3 tSUADSUB tHADSUB 1. Internal parameters are characterized, but not tested on every device. 2. RST resets VCO and all counters in PLL. 3. These parameters include the Adder Subtractor block in the path. Timing v. A 0.12 3-21 Lattice Semiconductor DC and Switching Characteristics LatticeXP2 Family Data Sheet EBR Timing Diagrams Figure 3-6. Read/Write Mode (Normal) CLKA CSA WEA ADA A0 tSU tH A1 A0 A1 A0 DIA D0 D1 tCO_EBR tCO_EBR D0 D1 tCO_EBR D0 DOA Invalid Data Note: Input data and address are registered at the positive edge of the clock and output data appears after the positive edge of the clock. Figure 3-7. Read/Write Mode with Input and Output Registers CLKA CSA WEA ADA A0 A1 A0 A1 A0 tSU tH DIA D0 D1 tCOO_EBR tCOO_EBR DOA (Regs) Mem(n) data from previous read output is only updated during a read cycle D0 D1 3-22 Lattice Semiconductor DC and Switching Characteristics LatticeXP2 Family Data Sheet Figure 3-8. Write Through (SP Read/Write on Port A, Input Registers Only) CLKA CSA WEA Three consecutive writes to A0 ADA A0 tSU tH A1 A0 DIA D0 tACCESS D1 tACCESS D2 tACCESS D3 D4 tACCESS DOA Data from Prev Read or Write D0 D1 D2 D3 D4 Note: Input data and address are registered at the positive edge of the clock and output data appears after the positive edge of the clock. 3-23 Lattice Semiconductor DC and Switching Characteristics LatticeXP2 Family Data Sheet LatticeXP2 Family Timing Adders1, 2, 3 Over Recommended Operating Conditions Buffer Type Input Adjusters LVDS25 BLVDS25 MLVDS RSDS LVPECL33 HSTL18_I HSTL18_II HSTL18D_I HSTL18D_II HSTL15_I HSTL15D_I SSTL33_I SSTL33_II SSTL33D_I SSTL33D_II SSTL25_I SSTL25_II SSTL25D_I SSTL25D_II SSTL18_I SSTL18_II SSTL18D_I SSTL18D_II LVTTL33 LVCMOS33 LVCMOS25 LVCMOS18 LVCMOS15 LVCMOS12 PCI33 Output Adjusters LVDS25E LVDS25 BLVDS25 MLVDS RSDS LVPECL33 HSTL18_I HSTL18_II HSTL18D_I HSTL18D_II LVDS 2.5 E4 LVDS 2.5 BLVDS 2.5 MLVDS 2.54 RSDS 2.54 LVPECL 3.34 HSTL_18 class I 8mA drive HSTL_18 class II Differential HSTL 18 class I 8mA drive Differential HSTL 18 class II -0.25 -0.25 -0.28 -0.28 -0.25 -0.37 -0.17 -0.29 -0.17 -0.29 0.02 0.02 0.00 0.00 0.02 -0.10 0.13 0.00 0.13 0.00 0.30 0.30 0.28 0.28 0.30 0.18 0.43 0.29 0.43 0.29 ns ns ns ns ns ns ns ns ns ns LVDS BLVDS LVDS RSDS LVPECL HSTL_18 class I HSTL_18 class II Differential HSTL 18 class I Differential HSTL 18 class II HSTL_15 class I Differential HSTL 15 class I SSTL_3 class I SSTL_3 class II Differential SSTL_3 class I Differential SSTL_3 class II SSTL_2 class I SSTL_2 class II Differential SSTL_2 class I Differential SSTL_2 class II SSTL_18 class I SSTL_18 class II Differential SSTL_18 class I Differential SSTL_18 class II LVTTL LVCMOS 3.3 LVCMOS 2.5 LVCMOS 1.8 LVCMOS 1.5 LVCMOS 1.2 3.3V PCI -0.26 -0.26 -0.26 -0.26 -0.26 -0.23 -0.23 -0.28 -0.28 -0.23 -0.28 -0.20 -0.20 -0.27 -0.27 -0.21 -0.21 -0.27 -0.27 -0.23 -0.23 -0.28 -0.28 -0.09 -0.09 0.00 -0.23 -0.20 -0.35 -0.09 -0.11 -0.11 -0.11 -0.11 -0.11 -0.08 -0.08 -0.13 -0.13 -0.09 -0.13 -0.04 -0.04 -0.11 -0.11 -0.06 -0.06 -0.12 -0.12 -0.08 -0.08 -0.13 -0.13 0.05 0.05 0.00 -0.07 -0.02 -0.20 0.05 0.04 0.04 0.04 0.04 0.04 0.07 0.07 0.02 0.02 0.06 0.01 0.12 0.12 0.04 0.04 0.10 0.10 0.03 0.03 0.07 0.07 0.02 0.02 0.18 0.18 0.00 0.09 0.16 -0.04 0.18 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Description -7 -6 -5 Units 3-24 Lattice Semiconductor DC and Switching Characteristics LatticeXP2 Family Data Sheet LatticeXP2 Family Timing Adders1, 2, 3 (Continued) Over Recommended Operating Conditions Buffer Type HSTL15_I HSTL15D_I SSTL33_I SSTL33_II SSTL33D_I SSTL33D_II SSTL25_I SSTL25_II SSTL25D_I SSTL25D_II SSTL18_I SSTL18_II SSTL18D_I SSTL18D_II LVTTL33_4mA LVTTL33_8mA LVTTL33_12mA LVTTL33_16mA LVTTL33_20mA LVCMOS33_4mA LVCMOS33_8mA LVCMOS33_12mA LVCMOS33_16mA LVCMOS33_20mA LVCMOS25_4mA LVCMOS25_8mA LVCMOS25_12mA LVCMOS25_16mA LVCMOS25_20mA LVCMOS18_4mA LVCMOS18_8mA LVCMOS18_12mA LVCMOS18_16mA LVCMOS15_4mA LVCMOS15_8mA LVCMOS12_2mA LVCMOS12_6mA LVCMOS33_4mA LVCMOS33_8mA LVCMOS33_12mA LVCMOS33_16mA LVCMOS33_20mA Description HSTL_15 class I 4mA drive Differential HSTL 15 class I 4mA drive SSTL_3 class I SSTL_3 class II Differential SSTL_3 class I Differential SSTL_3 class II SSTL_2 class I 8mA drive SSTL_2 class II 16mA drive Differential SSTL_2 class I 8mA drive Differential SSTL_2 class II 16mA drive SSTL_1.8 class I SSTL_1.8 class II 8mA drive Differential SSTL_1.8 class I Differential SSTL_1.8 class II 8mA drive LVTTL 4mA drive LVTTL 8mA drive LVTTL 12mA drive LVTTL 16mA drive LVTTL 20mA drive LVCMOS 3.3 4mA drive, fast slew rate LVCMOS 3.3 8mA drive, fast slew rate LVCMOS 3.3 12mA drive, fast slew rate LVCMOS 3.3 16mA drive, fast slew rate LVCMOS 3.3 20mA drive, fast slew rate LVCMOS 2.5 4mA drive, fast slew rate LVCMOS 2.5 8mA drive, fast slew rate LVCMOS 2.5 12mA drive, fast slew rate LVCMOS 2.5 16mA drive, fast slew rate LVCMOS 2.5 20mA drive, fast slew rate LVCMOS 1.8 4mA drive, fast slew rate LVCMOS 1.8 8mA drive, fast slew rate LVCMOS 1.8 12mA drive, fast slew rate LVCMOS 1.8 16mA drive, fast slew rate LVCMOS 1.5 4mA drive, fast slew rate LVCMOS 1.5 8mA drive, fast slew rate LVCMOS 1.2 2mA drive, fast slew rate LVCMOS 1.2 6mA drive, fast slew rate LVCMOS 3.3 4mA drive, slow slew rate LVCMOS 3.3 8mA drive, slow slew rate LVCMOS 3.3 12mA drive, slow slew rate LVCMOS 3.3 16mA drive, slow slew rate LVCMOS 3.3 20mA drive, slow slew rate -7 0.32 0.32 -0.25 -0.31 -0.25 -0.31 -0.25 -0.28 -0.25 -0.28 -0.17 -0.18 -0.17 -0.18 -0.37 -0.45 -0.52 -0.43 -0.46 -0.37 -0.45 -0.52 -0.43 -0.46 -0.42 -0.48 0.00 -0.45 -0.49 -0.46 -0.52 -0.56 -0.50 -0.45 -0.53 -0.46 -0.55 0.98 0.74 0.56 0.77 0.57 -6 0.69 0.69 0.05 -0.02 0.05 -0.02 0.02 0.00 0.02 0.00 0.13 0.12 0.13 0.12 -0.05 -0.18 -0.24 -0.14 -0.18 -0.05 -0.18 -0.24 -0.14 -0.18 -0.15 -0.21 0.00 -0.18 -0.22 -0.18 -0.25 -0.30 -0.24 -0.17 -0.26 -0.19 -0.29 1.41 1.16 0.97 1.19 0.98 -5 1.06 1.06 0.35 0.27 0.35 0.27 0.30 0.28 0.30 0.28 0.43 0.42 0.43 0.42 0.26 0.10 0.04 0.14 0.09 0.26 0.10 0.04 0.14 0.09 0.13 0.05 0.00 0.08 0.04 0.10 0.02 -0.03 0.03 0.11 0.00 0.08 -0.02 1.84 1.58 1.38 1.61 1.40 Units ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 3-25 Lattice Semiconductor DC and Switching Characteristics LatticeXP2 Family Data Sheet LatticeXP2 Family Timing Adders1, 2, 3 (Continued) Over Recommended Operating Conditions Buffer Type LVCMOS25_4mA LVCMOS25_8mA LVCMOS25_12mA LVCMOS25_16mA LVCMOS25_20mA LVCMOS18_4mA LVCMOS18_8mA LVCMOS18_12mA LVCMOS18_16mA LVCMOS15_4mA LVCMOS15_8mA LVCMOS12_2mA LVCMOS12_6mA PCI33 Description LVCMOS 2.5 4mA drive, slow slew rate LVCMOS 2.5 8mA drive, slow slew rate LVCMOS 2.5 12mA drive, slow slew rate LVCMOS 2.5 16mA drive, slow slew rate LVCMOS 2.5 20mA drive, slow slew rate LVCMOS 1.8 4mA drive, slow slew rate LVCMOS 1.8 8mA drive, slow slew rate LVCMOS 1.8 12mA drive, slow slew rate LVCMOS 1.8 16mA drive, slow slew rate LVCMOS 1.5 4mA drive, slow slew rate LVCMOS 1.5 8mA drive, slow slew rate LVCMOS 1.2 2mA drive, slow slew rate LVCMOS 1.2 6mA drive, slow slew rate 3.3V PCI -7 1.05 0.78 0.59 0.81 0.61 1.01 0.72 0.53 0.74 0.96 -0.53 0.90 -0.55 -0.29 -6 1.43 1.15 0.96 1.18 0.98 1.38 1.08 0.90 1.11 1.33 -0.26 1.27 -0.29 -0.01 -5 1.81 1.52 1.33 1.55 1.35 1.75 1.45 1.26 1.48 1.71 0.00 1.65 -0.02 0.26 Units ns ns ns ns ns ns ns ns ns ns ns ns ns ns 1. Timing Adders are characterized but not tested on every device. 2. LVCMOS timing measured with the load specified in Switching Test Condition table. 3. All other standards tested according to the appropriate specifications. 4. These timing adders are measured with the recommended resistor values. Timing v. A 0.12 3-26 Lattice Semiconductor DC and Switching Characteristics LatticeXP2 Family Data Sheet sysCLOCK PLL Timing Over Recommended Operating Conditions Parameter fIN fOUT fOUT2 fVCO fPFD tDT tCPA tPH 4 Description Input Clock Frequency (CLKI, CLKFB) Output Clock Frequency (CLKOP, CLKOS) K-Divider Output Frequency PLL VCO Frequency Phase Detector Input Frequency Output Clock Duty Cycle Coarse Phase Adjust Output Phase Accuracy CLKOK CLKOK2 Conditions Min. 10 10 0.078 3.3 435 10 Typ. -- -- -- -- -- -- 50 0 0 -- -- -- -- -- -- -- -- -- -- -- -- -- -- Max. 435 435 217.5 145 870 435 55 5 5 50 125 0.025 240 -- 50 100 200 10 -- -- 1 -- -- Units MHz MHz MHz MHz MHz MHz % % % ps ps UIPP ps ns s s ps ns ns ns ns ns ns AC Characteristics Default duty cycle selected 3 45 -5 -5 fOUT > 400 MHz tOPJIT1 tSK tOPW tLOCK2 tIPJIT tFBKDLY tHI tLO TR / tF tRSTKW tRSTW Output Clock Period Jitter Input Clock to Output Clock Skew Output Clock Pulse Width PLL Lock-in Time Input Clock Period Jitter External Feedback Delay Input Clock High Time Input Clock Low Time Input Clock Rise/Fall Time Reset Signal Pulse Width (RSTK) Reset Signal Pulse Width (RST) 90% to 90% 10% to 10% 10% to 90% 100 MHz < fOUT < 400 MHz fOUT < 100 MHz N/M = integer At 90% or 10% 25 to 435MHz 10 to 25MHz -- -- -- -- 1 -- -- -- -- 0.5 0.5 -- 10 500 1. Jitter sample is taken over 10,000 samples of the primary PLL output with clean reference clock. 2. Output clock is valid after tLOCK for PLL reset and dynamic delay adjustment. 3. Using LVDS output buffers. 4. Relative to CLKOP. Timing v. A 0.12 3-27 Lattice Semiconductor DC and Switching Characteristics LatticeXP2 Family Data Sheet LatticeXP2 sysCONFIG Port Timing Specifications Over Recommended Operating Conditions Parameter tICFG tVMC tPRGMRJ tPRGM tDINIT tDPPINIT tDPPDONE tIODISS tIOENSS tMWC tCFGX tCSSPI tCSCCLK tSOCDO tCSPID fMAXSPI tSUSPI tHSPI fMAXSPIS tRF tSTCO tSTOZ tSTSU tSTH tSTCKH tSTCKL tSTVO tSCS tSCSS tSCSH Description Minimum Vcc to INITN High Time from tICFG to valid Master CCLK PROGRAMN Pin Pulse Rejection PROGRAMN Low Time to Start Configuration PROGRAMN High to INITN High Delay Delay Time from PROGRAMN Low to INITN Low Delay Time from PROGRAMN Low to DONE Low User I/O Disable from PROGRAMN Low User I/O Enabled Time from CCLK Edge During Wake-up Sequence Additional Wake Master Clock Signals after DONE Pin High INITN High to CCLK Low INITN High to CSSPIN Low CCLK Low before CSSPIN Low CCLK Low to Output Valid CSSPIN[0:1] Low to First CCLK Edge Setup Time Max CCLK Frequency SOSPI Data Setup Time Before CCLK SOSPI Data Hold Time After CCLK Slave CCLK Frequency Rise and Fall Time Falling Edge of CCLK to SOSPI Active Falling Edge of CCLK to SOSPI Disable Data Setup Time (SISPI) Data Hold Time (SISPI) CCLK Clock Pulse Width, High CCLK Clock Pulse Width, Low Falling Edge of CCLK to Valid SOSPI Output CSSPISN High Time CSSPISN Setup Time CSSPISN Hold Time Min -- -- -- 50 -- -- -- -- -- 0 -- -- 0 -- 2cyc -- 7 10 -- 50 -- -- 8 10 0.02 0.02 -- 25 25 25 Max 50 2 12 -- 1 50 50 35 25 -- 1 2 -- 15 600+6cyc 20 -- -- 25 -- 20 20 -- -- 200 200 20 -- -- -- Units ms s ns ns ms ns ns ns ns cycles s s ns ns ns MHz ns ns MHz mV/ns ns ns ns ns s s ns ns ns ns sysCONFIG POR, Initialization and Wake Up sysCONFIG SPI Port (Master) sysCONFIG SPI Port (Slave) 3-28 Lattice Semiconductor DC and Switching Characteristics LatticeXP2 Family Data Sheet On-Chip Oscillator and Configuration Master Clock Characteristics Over Recommended Operating Conditions Parameter Master Clock Frequency Duty Cycle Timing v. A 0.12 Min. Selected value -30% 40 Max. Selected value +30% 60 Units MHz % Figure 3-9. Master SPI Configuration Waveforms Capture CR0 VCC PROGRAMN DONE INITN Capture CFGx CSSPIN 0 CCLK SISPI SOSPI Opcode Address Ignore Valid Bitstream 1 2 3 ... 7 8 9 10 ... 31 32 33 34 ... 127 128 3-29 Lattice Semiconductor DC and Switching Characteristics LatticeXP2 Family Data Sheet Flash Download Time (from On-Chip Flash to SRAM) Over Recommended Operating Conditions Symbol Parameter XP2-5 PROGRAMN Low-toHigh. Transition to Done XP2-17 High. XP2-30 tREFRESH Power-up refresh when PROGRAMN is pulled up to VCC (VCC=VCC Min) XP2-40 XP2-5 XP2-8 XP2-17 XP2-30 XP2-40 XP2-8 Min. -- -- -- -- -- -- -- -- -- -- Typ. 1.8 1.9 1.7 2.0 2.0 1.8 1.9 1.7 2.0 2.0 Max. 2.1 2.3 2.0 2.1 2.3 2.1 2.3 2.0 2.1 2.3 Units ms ms ms ms ms ms ms ms ms ms Flash Program Time Over Recommended Operating Conditions Program Time Device XP2-5 XP2-8 XP2-17 XP2-30 XP2-40 1.2M 2.0M 3.6M 6.0M 8.0M Flash Density TAG Main Array TAG Main Array TAG Main Array TAG Main Array TAG Main Array Typ. 1.0 1.1 1.0 1.4 1.0 1.8 2.0 3.0 2.0 4.0 Units ms s ms s ms s ms s ms s Flash Erase Time Over Recommended Operating Conditions Erase Time Device XP2-5 XP2-8 XP2-17 XP2-30 XP2-40 1.2M 2.0M 3.6M 6.0M 8.0M Flash Density TAG Main Array TAG Main Array TAG Main Array TAG Main Array TAG Main Array Typ. 1.0 3.0 1.0 4.0 1.0 5.0 2.0 7.0 2.0 9.0 Units s s s s s s s s s s 3-30 Lattice Semiconductor DC and Switching Characteristics LatticeXP2 Family Data Sheet FlashBAK Time (from EBR to Flash) Over Recommended Operating Conditions Device XP2-5 XP2-8 XP2-17 XP2-30 XP2-40 EBR Density (Bits) 166K 221K 276K 387K 885K Time (Typ.) 1.5 1.5 1.5 2.0 3.0 Units s s s s s JTAG Port Timing Specifications Over Recommended Operating Conditions Symbol fMAX tBTCP tBTCPH tBTCPL tBTS tBTH tBTRF tBTCO tBTCODIS tBTCOEN tBTCRS tBTCRH tBUTCO tBTUODIS tBTUPOEN Timing v. A 0.12 Parameter TCK Clock Frequency TCK [BSCAN] clock pulse width TCK [BSCAN] clock pulse width high TCK [BSCAN] clock pulse width low TCK [BSCAN] setup time TCK [BSCAN] hold time TCK [BSCAN] rise/fall time TAP controller falling edge of clock to valid output TAP controller falling edge of clock to valid disable TAP controller falling edge of clock to valid enable BSCAN test capture register setup time BSCAN test capture register hold time BSCAN test update register, falling edge of clock to valid output BSCAN test update register, falling edge of clock to valid disable BSCAN test update register, falling edge of clock to valid enable Min. -- 40 20 20 8 10 50 -- -- -- 8 25 -- -- -- Max. 25 -- -- -- -- -- -- 10 10 10 -- -- 25 25 25 Units MHz ns ns ns ns ns mV/ns ns ns ns ns ns ns ns ns 3-31 Lattice Semiconductor Figure 3-10. JTAG Port Timing Waveforms TMS DC and Switching Characteristics LatticeXP2 Family Data Sheet TDI tBTS tBTCPH TCK tBTCPL tBTH tBTCP tBTCOEN TDO Valid Data tBTCO Valid Data tBTCODIS tBTCRS Data to be captured from I/O tBTUPOEN Data to be driven out to I/O tBTCRH Data Captured tBUTCO Valid Data tBTUODIS Valid Data 3-32 Lattice Semiconductor DC and Switching Characteristics LatticeXP2 Family Data Sheet Switching Test Conditions Figure 3-11 shows the output test load that is used for AC testing. The specific values for resistance, capacitance, voltage, and other test conditions are shown in Table 3-6. Figure 3-11. Output Test Load, LVTTL and LVCMOS Standards VT R1 DUT R2 CL* Test Poi nt *CL Includes Test Fixture and Probe Capacitance Table 3-6. Test Fixture Required Components, Non-Terminated Interfaces Test Condition R1 R2 CL Timing Ref. LVCMOS 3.3 = 1.5V LVCMOS 2.5 = VCCIO/2 LVTTL and other LVCMOS settings (L -> H, H -> L) VT -- -- -- -- -- -- VCCIO -- VCCIO 1M 0pF LVCMOS 1.8 = VCCIO/2 LVCMOS 1.5 = VCCIO/2 LVCMOS 1.2 = VCCIO/2 LVCMOS 2.5 I/O (Z -> H) LVCMOS 2.5 I/O (Z -> L) LVCMOS 2.5 I/O (H -> Z) LVCMOS 2.5 I/O (L -> Z) 1M VCCIO/2 VCCIO/2 VOH - 0.10 VOL + 0.10 100 100 Note: Output test conditions for all other interfaces are determined by the respective standards. 3-33 LatticeXP2 Family Data Sheet Pinout Information June 2008 Data Sheet DS1009 Signal Descriptions Signal Name General Purpose [Edge] indicates the edge of the device on which the pad is located. Valid edge designations are L (Left), B (Bottom), R (Right), T (Top). [Row/Column Number] indicates the PFU row or the column of the device on which the PIC exists. When Edge is T (Top) or B (Bottom), only need to specify Row Number. When Edge is L (Left) or R (Right), only need to specify Column Number. P[Edge] [Row/Column Number*]_[A/B] I/O [A/B] indicates the PIO within the PIC to which the pad is connected. Some of these user-programmable pins are shared with special function pins. These pins, when not used as special purpose pins, can be programmed as I/Os for user logic. During configuration the user-programmable I/Os are tri-stated with an internal pull-up resistor enabled. If any pin is not used (or not bonded to a package pin), it is also tri-stated with an internal pull-up resistor enabled after configuration. GSRN NC GND VCC VCCAUX VCCPLL VCCIOx VREF1_x, VREF2_x I -- -- -- -- -- -- -- Global RESET signal (active low). Any I/O pin can be GSRN. No connect. Ground. Dedicated pins. Power supply pins for core logic. Dedicated pins. Auxiliary power supply pin. This dedicated pin powers all the differential and referenced input buffers. PLL supply pins. csBGA, PQFP and TQFP packages only. Dedicated power supply pins for I/O bank x. Reference supply pins for I/O bank x. Pre-determined pins in each bank are assigned as VREF inputs. When not used, they may be used as I/O pins. Power supply pin for PLL: LLC, LRC, URC, ULC, num = row from center. General Purpose PLL (GPLL) input pads: LLC, LRC, URC, ULC, num = row from center, T = true and C = complement, index A,B,C...at each side. Optional feedback GPLL input pads: LLC, LRC, URC, ULC, num = row from center, T = true and C = complement, index A,B,C...at each side. Primary Clock pads, T = true and C = complement, n per side, indexed by bank and 0,1,2,3 within bank. DQS input pads: T (Top), R (Right), B (Bottom), L (Left), DQS, num = ball function number. Any pad can be configured to be output. Test Mode Select input, used to control the 1149.1 state machine. Pull-up is enabled during configuration. Test Clock input pin, used to clock the 1149.1 state machine. No pull-up enabled. Test Data in pin. Used to load data into device using 1149.1 state machine. After power-up, this TAP port can be activated for configuration by sending appropriate command. (Note: once a configuration port is selected it is locked. Another configuration port cannot be selected until the power-up sequence). Pull-up is enabled during configuration. I/O Description PLL and Clock Functions (Used as user programmable I/O pins when not in use for PLL or clock pins) [LOC][num]_VCCPLL [LOC][num]_GPLL[T, C]_IN_A [LOC][num]_GPLL[T, C]_FB_A PCLK[T, C]_[n:0]_[3:0] [LOC]DQS[num] Test and Programming (Dedicated Pins) TMS TCK I I -- I I I I TDI I (c) 2008 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. www.latticesemi.com 4-1 Pinout Information_01.5 Lattice Semiconductor Pinout Information LatticeXP2 Family Data Sheet Signal Descriptions (Cont.) Signal Name TDO VCCJ I/O O -- Description Output pin. Test Data Out pin used to shift data out of a device using 1149.1. Power supply pin for JTAG Test Access Port. Mode pins used to specify configuration mode values latched on rising edge of INITN. During configuration, an internal pull-up is enabled. Open Drain pin. Indicates the FPGA is ready to be configured. During configuration, a pull-up is enabled. Initiates configuration sequence when asserted low. This pin always has an active pull-up. Open Drain pin. Indicates that the configuration sequence is complete, and the startup sequence is in progress. Configuration Clock for configuring an FPGA in sysCONFIG mode. Input data pin in slave SPI mode and Output data pin in Master SPI mode. Output data pin in slave SPI mode and Input data pin in Master SPI mode. Chip select for external SPI Flash memory in Master SPI mode. This pin has a weak internal pull-up. Chip select in Slave SPI mode. This pin has a weak internal pull-up. Test Output Enable tristates all I/O pins when driven low. This pin has a weak internal pull-up, but when not used an external pull-up to VCC is recommended. Configuration Pads (Used during sysCONFIG) CFG[1:0] INITN1 PROGRAMN DONE CCLK SISPI 2 2 I I/O I I/O I/O I/O I/O SOSPI CSSPIN 2 O I I CSSPISN TOE 1. If not actively driven, the internal pull-up may not be sufficient. An external pull-up resistor of 4.7k to 10k ohms is recommended. 2. When using the device in Master SPI mode, it must be mutually exclusive from JTAG operations (i.e. TCK tied to GND) or the JTAG TCK must be free-running when used in a system JTAG test environment. If Master SPI mode is used in conjunction with a JTAG download cable, the device power cycle is required after the cable is unplugged. 4-2 Lattice Semiconductor Pinout Information LatticeXP2 Family Data Sheet PICs and DDR Data (DQ) Pins Associated with the DDR Strobe (DQS) Pin PICs Associated with DQS Strobe PIO Within PIC A B A B A B A B A B A B A B A B A B A B A B A B A B A B A B A B A B DDR Strobe (DQS) and Data (DQ) Pins DQ DQ DQ DQ DQ DQ DQ DQ [Edge]DQSn DQ DQ DQ DQ DQ DQ DQ DQ DQ DQ DQ DQ DQ DQ DQ [Edge]DQSn DQ DQ DQ DQ DQ DQ DQ DQ DQ For Left and Right Edges of the Device P[Edge] [n-4] P[Edge] [n-3] P[Edge] [n-2] P[Edge] [n-1] P[Edge] [n] P[Edge] [n+1] P[Edge] [n+2] P[Edge] [n+3] For Top and Bottom Edges of the Device P[Edge] [n-4] P[Edge] [n-3] P[Edge] [n-2] P[Edge] [n-1] P[Edge] [n] P[Edge] [n+1] P[Edge] [n+2] P[Edge] [n+3] P[Edge] [n+4] Notes: 1. "n" is a row PIC number. 2. The DDR interface is designed for memories that support one DQS strobe up to 16 bits of data for the left and right edges and up to 18 bits of data for the top and bottom edges. In some packages, all the potential DDR data (DQ) pins may not be available. PIC numbering definitions are provided in the "Signal Names" column of the Signal Descriptions table. 4-3 Lattice Semiconductor Pinout Information LatticeXP2 Family Data Sheet Pin Information Summary XP2-5 Pin Type Single Ended User I/O Differential Pair User I/O Normal Highspeed TAP Configuration Muxed Dedicated Non Configuration Vcc Vccaux VCCPLL Bank0 Bank1 Bank2 VCCIO Bank3 Bank4 Bank5 Bank6 Bank7 GND, GND0-GND7 NC Bank0 Bank1 Bank2 Single Ended/ Differential I/O per Bank Bank3 Bank4 Bank5 Bank6 Bank7 Bank0 Bank1 Bank2 True LVDS Pairs Bank3 Bonding Out per Bank4 Bank Bank5 Bank6 Bank7 Bank0 Bank1 Bank2 DDR Banks Bank3 Bonding Out per 1 Bank4 I/O Bank Bank5 Bank6 Bank7 Muxed Dedicated XP2-8 XP2-17 XP2-30 XP2-40 132 144 208 256 132 144 208 256 208 256 484 256 484 672 484 672 csBGA TQFP PQFP ftBGA csBGA TQFP PQFP ftBGA PQFP ftBGA fpBGA ftBGA fpBGA fpBGA fpBGA fpBGA 86 35 8 5 9 1 5 1 6 4 2 2 1 2 1 1 2 1 2 15 18/9 4/2 16/8 4/2 8/4 14/7 6/3 16/8 0 0 3 1 0 0 1 3 1 0 1 0 0 1 0 1 100 39 11 5 9 1 5 1 4 4 2 2 1 2 1 1 2 1 2 15 146 57 16 5 9 1 7 1 9 4 2 2 2 2 2 2 2 2 2 20 4 172 66 20 5 9 1 7 1 6 4 2 2 2 2 2 2 2 2 20 31 86 35 8 5 9 1 7 1 6 4 2 2 1 2 1 1 2 1 2 15 18/9 4/2 16/8 4/2 8/4 14/7 6/3 16/8 0 0 3 1 0 0 1 3 1 0 1 0 0 1 0 1 100 39 11 5 9 1 7 1 4 4 2 2 1 2 1 1 2 1 2 15 146 57 16 5 9 1 9 1 9 4 2 2 2 2 2 2 2 2 2 22 2 201 77 23 5 9 1 9 1 6 4 2 2 2 2 2 2 2 2 20 2 146 57 16 5 9 1 11 1 9 4 4 2 2 2 2 2 2 2 2 22 201 77 23 5 9 1 11 1 6 4 2 2 2 2 2 2 2 2 20 2 358 135 44 5 9 1 21 1 16 8 4 4 4 4 4 4 4 4 56 7 52/26 36/18 46/23 44/22 36/18 52/26 46/23 46/23 0 0 11 11 0 0 11 11 3 2 2 2 2 3 2 2 201 77 23 5 9 1 7 1 6 4 2 2 2 2 2 2 2 2 20 2 28/14 22/11 26/13 24/12 26/13 24/12 27/13 24/12 0 0 6 6 0 0 6 5 1 1 1 1 1 1 1 1 363 137 44 5 9 1 11 1 16 8 4 4 4 4 4 4 4 4 56 2 52/26 36/18 46/23 46/23 38/19 53/26 46/23 46/23 0 0 11 11 0 0 11 11 2 2 3 3 2 2 3 3 472 180 56 5 9 1 13 1 20 8 4 4 4 4 4 4 4 4 64 69 70/35 54/27 56/28 56/28 54/27 70/35 56/28 56/28 0 0 14 14 0 0 14 14 4 3 3 3 3 4 3 3 363 137 44 5 9 1 11 1 16 8 4 4 4 4 4 4 4 4 56 2 52/26 36/18 46/23 46/23 38/19 53/26 46/23 46/23 0 0 11 11 0 0 11 11 2 2 3 3 2 2 3 3 540 204 66 5 9 1 13 1 20 8 4 4 4 4 4 4 4 4 64 1 70/35 70/35 64/32 66/33 70/35 70/35 66/33 64/32 0 0 16 17 0 0 17 16 4 4 4 4 4 4 4 4 20/10 20/10 26/13 6/3 18/9 4/2 8/4 18/9 8/4 18/9 0 0 4 1 0 0 2 4 1 0 1 0 0 1 0 1 18/9 18/9 16/8 18/9 18/9 22/11 20/10 18/9 20/10 20/10 28/14 20/10 28/14 6/3 18/9 4/2 8/4 18/9 8/4 18/9 0 0 4 1 0 0 2 4 1 0 1 0 0 1 0 1 18/9 18/9 16/8 18/9 22/11 26/13 24/12 26/13 18/9 18/9 16/8 18/9 22/11 26/13 24/12 26/13 20/10 24/12 18/9 18/9 0 0 4 4 0 0 4 4 1 1 1 1 1 1 1 1 22/11 22/11 0 0 5 5 0 0 5 5 1 1 1 1 1 1 1 1 20/10 24/12 20/10 24/12 18/9 18/9 0 0 4 4 0 0 4 4 1 1 1 1 1 1 1 1 27/13 24/12 0 0 6 6 0 0 6 5 1 1 1 1 1 1 1 1 18/9 18/9 0 0 4 4 0 0 4 4 1 1 1 1 1 1 1 1 27/13 24/12 0 0 6 6 0 0 6 5 1 1 1 1 1 1 1 1 4-4 Lattice Semiconductor Pinout Information LatticeXP2 Family Data Sheet Pin Information Summary (Cont.) XP2-5 Pin Type Bank0 Bank1 Bank2 PCI capable I/Os Bank3 Bonding Out per Bank4 Bank Bank5 Bank6 Bank7 XP2-8 XP2-17 XP2-30 XP2-40 132 144 208 256 132 144 208 256 208 256 484 256 484 672 484 672 csBGA TQFP PQFP ftBGA csBGA TQFP PQFP ftBGA PQFP ftBGA fpBGA ftBGA fpBGA fpBGA fpBGA fpBGA 18 4 0 0 8 14 0 0 20 6 0 0 8 18 0 0 20 18 0 0 18 20 0 0 26 18 0 0 18 24 0 0 18 4 0 0 8 14 0 0 20 6 0 0 8 18 0 0 20 18 0 0 18 20 0 0 28 22 0 0 26 24 0 0 20 18 0 0 18 20 0 0 28 22 0 0 26 24 0 0 52 36 0 0 36 52 0 0 28 22 0 0 26 24 0 0 52 36 0 0 38 53 0 0 70 54 0 0 54 70 0 0 52 36 0 0 38 53 0 0 70 70 0 0 70 70 0 0 1. Minimum requirement to implement a fully functional 8-bit wide DDR bus. Available DDR interface consists of at least 12 I/Os (1 DQS + 1 DQSB + 8 DQs + 1 DM + Bank VREF1). Logic Signal Connections Package pinout information can be found under "Data Sheets" on the LatticeXP2 product pages on the Lattice website at www.latticesemi.com/products/fpga/XP2 and in the Lattice ispLEVER software. Thermal Management Thermal management is recommended as part of any sound FPGA design methodology. To assess the thermal characteristics of a system, Lattice specifies a maximum allowable junction temperature in all device data sheets. Designers must complete a thermal analysis of their specific design to ensure that the device and package do not exceed the junction temperature limits. Refer to the Thermal Management document to find the device/package specific thermal values. For further information regarding Thermal Management, refer to the Thermal Management document located on the Lattice website at www.latticesemi.com. For Further Information * Technical Note TN1139 - Power Estimation and Management for LatticeXP2 Devices * Power Calculator tool included with Lattice's ispLEVER design tool, or as a standalone download from www.latticesemi.com/software 4-5 LatticeXP2 Family Data Sheet Ordering Information August 2008 Data Sheet DS1009 Part Number Description LFXP2 - XX E - X XXXXX X Device Family XP2 Logic Capacity 5 = 5K LUTs 8 = 8K LUTs 17 = 17K LUTs 30 = 30K LUTs 40 = 40K LUTs Supply Voltage E = 1.2V Speed 5 = Slowest 6 7 = Fastest Grade C = Commercial I = Industrial Package M132 = 132-ball csBGA FT256 = 256-ball ftBGA F484 = 484-ball fpBGA F672 = 672-ball fpBGA MN132 = 132-ball Lead-Free csBGA TN144 = 144-pin Lead-Free TQFP QN208 = 208-pin Lead-Free PQFP FTN256 = 256-ball Lead-Free ftBGA FN484 = 484-ball Lead-Free fpBGA FN672 = 672-ball Lead-Free fpBGA Ordering Information The LatticeXP2 devices are marked with a single temperature grade, either Commercial or Industrial, as shown below. XP2 XP2 LFXP2-17E 7FT256C Datecode LFXP2-17E 6FT256I Datecode (c) 2008 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. www.latticesemi.com 5-1 Order Info_01.2 Lattice Semiconductor Lead-Free Packaging Commercial Part Number LFXP2-5E-5MN132C LFXP2-5E-6MN132C LFXP2-5E-7MN132C LFXP2-5E-5TN144C LFXP2-5E-6TN144C LFXP2-5E-7TN144C LFXP2-5E-5QN208C LFXP2-5E-6QN208C LFXP2-5E-7QN208C LFXP2-5E-5FTN256C LFXP2-5E-6FTN256C LFXP2-5E-7FTN256C Voltage 1.2V 1.2V 1.2V 1.2V 1.2V 1.2V 1.2V 1.2V 1.2V 1.2V 1.2V 1.2V Grade -5 -6 -7 -5 -6 -7 -5 -6 -7 -5 -6 -7 Package Lead-Free csBGA Lead-Free csBGA Lead-Free csBGA Lead-Free TQFP Lead-Free TQFP Lead-Free TQFP Lead-Free PQFP Lead-Free PQFP Lead-Free PQFP Lead-Free ftBGA Lead-Free ftBGA Lead-Free ftBGA Ordering Information LatticeXP2 Family Data Sheet Pins 132 132 132 144 144 144 208 208 208 256 256 256 Temp. COM COM COM COM COM COM COM COM COM COM COM COM LUTs (k) 5 5 5 5 5 5 5 5 5 5 5 5 Part Number LFXP2-8E-5MN132C LFXP2-8E-6MN132C LFXP2-8E-7MN132C LFXP2-8E-5TN144C LFXP2-8E-6TN144C LFXP2-8E-7TN144C LFXP2-8E-5QN208C LFXP2-8E-6QN208C LFXP2-8E-7QN208C LFXP2-8E-5FTN256C LFXP2-8E-6FTN256C LFXP2-8E-7FTN256C Voltage 1.2V 1.2V 1.2V 1.2V 1.2V 1.2V 1.2V 1.2V 1.2V 1.2V 1.2V 1.2V Grade -5 -6 -7 -5 -6 -7 -5 -6 -7 -5 -6 -7 Package Lead-Free csBGA Lead-Free csBGA Lead-Free csBGA Lead-Free TQFP Lead-Free TQFP Lead-Free TQFP Lead-Free PQFP Lead-Free PQFP Lead-Free PQFP Lead-Free ftBGA Lead-Free ftBGA Lead-Free ftBGA Pins 132 132 132 144 144 144 208 208 208 256 256 256 Temp. COM COM COM COM COM COM COM COM COM COM COM COM LUTs (k) 8 8 8 8 8 8 8 8 8 8 8 8 Part Number LFXP2-17E-5QN208C LFXP2-17E-6QN208C LFXP2-17E-7QN208C LFXP2-17E-5FTN256C LFXP2-17E-6FTN256C LFXP2-17E-7FTN256C LFXP2-17E-5FN484C LFXP2-17E-6FN484C LFXP2-17E-7FN484C Voltage 1.2V 1.2V 1.2V 1.2V 1.2V 1.2V 1.2V 1.2V 1.2V Grade -5 -6 -7 -5 -6 -7 -5 -6 -7 Package Lead-Free PQFP Lead-Free PQFP Lead-Free PQFP Lead-Free ftBGA Lead-Free ftBGA Lead-Free ftBGA Lead-Free fpBGA Lead-Free fpBGA Lead-Free fpBGA Pins 208 208 208 256 256 256 484 484 484 Temp. COM COM COM COM COM COM COM COM COM LUTs (k) 17 17 17 17 17 17 17 17 17 5-2 Lattice Semiconductor Ordering Information LatticeXP2 Family Data Sheet Part Number LFXP2-30E-5FTN256C LFXP2-30E-6FTN256C LFXP2-30E-7FTN256C LFXP2-30E-5FN484C LFXP2-30E-6FN484C LFXP2-30E-7FN484C LFXP2-30E-5FN672C LFXP2-30E-6FN672C LFXP2-30E-7FN672C Voltage 1.2V 1.2V 1.2V 1.2V 1.2V 1.2V 1.2V 1.2V 1.2V Grade -5 -6 -7 -5 -6 -7 -5 -6 -7 Package Lead-Free ftBGA Lead-Free ftBGA Lead-Free ftBGA Lead-Free fpBGA Lead-Free fpBGA Lead-Free fpBGA Lead-Free fpBGA Lead-Free fpBGA Lead-Free fpBGA Pins 256 256 256 484 484 484 672 672 672 Temp. COM COM COM COM COM COM COM COM COM LUTs (k) 30 30 30 30 30 30 30 30 30 Part Number LFXP2-40E-5FN484C LFXP2-40E-6FN484C LFXP2-40E-7FN484C LFXP2-40E-5FN672C LFXP2-40E-6FN672C LFXP2-40E-7FN672C Voltage 1.2V 1.2V 1.2V 1.2V 1.2V 1.2V Grade -5 -6 -7 -5 -6 -7 Package Lead-Free fpBGA Lead-Free fpBGA Lead-Free fpBGA Lead-Free fpBGA Lead-Free fpBGA Lead-Free fpBGA Pins 484 484 484 672 672 672 Temp. COM COM COM COM COM COM LUTs (k) 40 40 40 40 40 40 Industrial Part Number LFXP2-5E-5MN132I LFXP2-5E-6MN132I LFXP2-5E-5TN144I LFXP2-5E-6TN144I LFXP2-5E-5QN208I LFXP2-5E-6QN208I LFXP2-5E-5FTN256I LFXP2-5E-6FTN256I Voltage 1.2V 1.2V 1.2V 1.2V 1.2V 1.2V 1.2V 1.2V Grade -5 -6 -5 -6 -5 -6 -5 -6 Package Lead-Free csBGA Lead-Free csBGA Lead-Free TQFP Lead-Free TQFP Lead-Free PQFP Lead-Free PQFP Lead-Free ftBGA Lead-Free ftBGA Pins 132 132 144 144 208 208 256 256 Temp. IND IND IND IND IND IND IND IND LUTs (k) 5 5 5 5 5 5 5 5 Part Number LFXP2-8E-5MN132I LFXP2-8E-6MN132I LFXP2-8E-5TN144I LFXP2-8E-6TN144I LFXP2-8E-5QN208I LFXP2-8E-6QN208I LFXP2-8E-5FTN256I LFXP2-8E-6FTN256I Voltage 1.2V 1.2V 1.2V 1.2V 1.2V 1.2V 1.2V 1.2V Grade -5 -6 -5 -6 -5 -6 -5 -6 Package Lead-Free csBGA Lead-Free csBGA Lead-Free TQFP Lead-Free TQFP Lead-Free PQFP Lead-Free PQFP Lead-Free ftBGA Lead-Free ftBGA Pins 132 132 144 144 208 208 256 256 Temp. IND IND IND IND IND IND IND IND LUTs (k) 8 8 8 8 8 8 8 8 5-3 Lattice Semiconductor Ordering Information LatticeXP2 Family Data Sheet Part Number LFXP2-17E-5QN208I LFXP2-17E-6QN208I LFXP2-17E-5FTN256I LFXP2-17E-6FTN256I LFXP2-17E-5FN484I LFXP2-17E-6FN484I Voltage 1.2V 1.2V 1.2V 1.2V 1.2V 1.2V Grade -5 -6 -5 -6 -5 -6 Package Lead-Free PQFP Lead-Free PQFP Lead-Free ftBGA Lead-Free ftBGA Lead-Free fpBGA Lead-Free fpBGA Pins 208 208 256 256 484 484 Temp. IND IND IND IND IND IND LUTs (k) 17 17 17 17 17 17 Part Number LFXP2-30E-5FTN256I LFXP2-30E-6FTN256I LFXP2-30E-5FN484I LFXP2-30E-6FN484I LFXP2-30E-5FN672I LFXP2-30E-6FN672I Voltage 1.2V 1.2V 1.2V 1.2V 1.2V 1.2V Grade -5 -6 -5 -6 -5 -6 Package Lead-Free ftBGA Lead-Free ftBGA Lead-Free fpBGA Lead-Free fpBGA Lead-Free fpBGA Lead-Free fpBGA Pins 256 256 484 484 672 672 Temp. IND IND IND IND IND IND LUTs (k) 30 30 30 30 30 30 Part Number LFXP2-40E-5FN484I LFXP2-40E-6FN484I LFXP2-40E-5FN672I LFXP2-40E-6FN672I Voltage 1.2V 1.2V 1.2V 1.2V Grade -5 -6 -5 -6 Package Lead-Free fpBGA Lead-Free fpBGA Lead-Free fpBGA Lead-Free fpBGA Pins 484 484 672 672 Temp. IND IND IND IND LUTs (k) 40 40 40 40 5-4 Lattice Semiconductor Conventional Packaging Commercial Part Number LFXP2-5E-5M132C LFXP2-5E-6M132C LFXP2-5E-7M132C LFXP2-5E-5FT256C LFXP2-5E-6FT256C LFXP2-5E-7FT256C Voltage 1.2V 1.2V 1.2V 1.2V 1.2V 1.2V Grade -5 -6 -7 -5 -6 -7 Package csBGA csBGA csBGA ftBGA ftBGA ftBGA Ordering Information LatticeXP2 Family Data Sheet Pins 132 132 132 256 256 256 Temp. COM COM COM COM COM COM LUTs (k) 5 5 5 5 5 5 Part Number LFXP2-8E-5M132C LFXP2-8E-6M132C LFXP2-8E-7M132C LFXP2-8E-5FT256C LFXP2-8E-6FT256C LFXP2-8E-7FT256C Voltage 1.2V 1.2V 1.2V 1.2V 1.2V 1.2V Grade -5 -6 -7 -5 -6 -7 Package csBGA csBGA csBGA ftBGA ftBGA ftBGA Pins 132 132 132 256 256 256 Temp. COM COM COM COM COM COM LUTs (k) 8 8 8 8 8 8 Part Number LFXP2-17E-5FT256C LFXP2-17E-6FT256C LFXP2-17E-7FT256C LFXP2-17E-5F484C LFXP2-17E-6F484C LFXP2-17E-7F484C Voltage 1.2V 1.2V 1.2V 1.2V 1.2V 1.2V Grade -5 -6 -7 -5 -6 -7 Package ftBGA ftBGA ftBGA fpBGA fpBGA fpBGA Pins 256 256 256 484 484 484 Temp. COM COM COM COM COM COM LUTs (k) 17 17 17 17 17 17 Part Number LFXP2-30E-5FT256C LFXP2-30E-6FT256C LFXP2-30E-7FT256C LFXP2-30E-5F484C LFXP2-30E-6F484C LFXP2-30E-7F484C LFXP2-30E-5F672C LFXP2-30E-6F672C LFXP2-30E-7F672C Voltage 1.2V 1.2V 1.2V 1.2V 1.2V 1.2V 1.2V 1.2V 1.2V Grade -5 -6 -7 -5 -6 -7 -5 -6 -7 Package ftBGA ftBGA ftBGA fpBGA fpBGA fpBGA fpBGA fpBGA fpBGA Pins 256 256 256 484 484 484 672 672 672 Temp. COM COM COM COM COM COM COM COM COM LUTs (k) 30 30 30 30 30 30 30 30 30 5-5 Lattice Semiconductor Ordering Information LatticeXP2 Family Data Sheet Part Number LFXP2-40E-5F484C LFXP2-40E-6F484C LFXP2-40E-7F484C LFXP2-40E-5F672C LFXP2-40E-6F672C LFXP2-40E-7F672C Voltage 1.2V 1.2V 1.2V 1.2V 1.2V 1.2V Grade -5 -6 -7 -5 -6 -7 Package fpBGA fpBGA fpBGA fpBGA fpBGA fpBGA Pins 484 484 484 672 672 672 Temp. COM COM COM COM COM COM LUTs (k) 40 40 40 40 40 40 Industrial Part Number LFXP2-5E-5M132I LFXP2-5E-6M132I LFXP2-5E-6FT256I Voltage 1.2V 1.2V 1.2V Grade -5 -6 -6 Package csBGA csBGA ftBGA Pins 132 132 256 Temp. IND IND IND LUTs (k) 5 5 5 Part Number LFXP2-8E-5M132I LFXP2-8E-6M132I LFXP2-5E-5FT256I LFXP2-8E-5FT256I LFXP2-8E-6FT256I Voltage 1.2V 1.2V 1.2V 1.2V 1.2V Grade -5 -6 -5 -5 -6 Package csBGA csBGA ftBGA ftBGA ftBGA Pins 132 132 256 256 256 Temp. IND IND IND IND IND LUTs (k) 8 8 5 8 8 Part Number LFXP2-17E-5FT256I LFXP2-17E-6FT256I LFXP2-17E-5F484I LFXP2-17E-6F484I Voltage 1.2V 1.2V 1.2V 1.2V Grade -5 -6 -5 -6 Package ftBGA ftBGA fpBGA fpBGA Pins 256 256 484 484 Temp. IND IND IND IND LUTs (k) 17 17 17 17 Part Number LFXP2-30E-5FT256I LFXP2-30E-6FT256I LFXP2-30E-5F484I LFXP2-30E-6F484I LFXP2-30E-5F672I LFXP2-30E-6F672I Voltage 1.2V 1.2V 1.2V 1.2V 1.2V 1.2V Grade -5 -6 -5 -6 -5 -6 Package ftBGA ftBGA fpBGA fpBGA fpBGA fpBGA Pins 256 256 484 484 672 672 Temp. IND IND IND IND IND IND LUTs (k) 30 30 30 30 30 30 5-6 Lattice Semiconductor Ordering Information LatticeXP2 Family Data Sheet Part Number LFXP2-40E-5F484I LFXP2-40E-6F484I LFXP2-40E-5F672I LFXP2-40E-6F672I Voltage 1.2V 1.2V 1.2V 1.2V Grade -5 -6 -5 -6 Package fpBGA fpBGA fpBGA fpBGA Pins 484 484 672 672 Temp. IND IND IND IND LUTs (k) 40 40 40 40 5-7 LatticeXP2 Family Data Sheet Supplemental Information May 2007 Data Sheet DS1009 For Further Information A variety of technical notes for the LatticeXP2 FPGA family are available on the Lattice Semiconductor web site at www.latticesemi.com/products/fpga/XP2. * * * * * * * * * * * LatticeXP2 sysIO Usage Guide (TN1136) LatticeXP2 Memory Usage Guide (TN1137) LatticeXP2 High Speed I/O Interface (TN1138) LatticeXP2 sysCLOCK PLL Design and Usage Guide (TN1126) Power Estimation and Management for LatticeXP2 Devices (TN1139) LatticeXP2 sysDSP Usage Guide (TN1140) LatticeXP2 sysCONFIG Usage Guide (TN1141) LatticeXP2 Configuration Encryption and Security Usage Guide (TN1142) Minimizing System Interruption During Configuration Using TransFR Technology (TN1087) LatticeXP2 Dual Boot Usage Guide (TN1144) LatticeXP2 Soft Error Detection (SED) Usage Guide (TN1130) For further information on interface standards refer to the following web sites: * JEDEC Standards (LVTTL, LVCMOS, SSTL, HSTL): www.jedec.org * PCI: www.pcisig.com (c) 2007 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. www.latticesemi.com 6-1 Further Info_01.1 LatticeXP2 Family Data Sheet Revision History August 2008 Data Sheet DS1009 Revision History Date May 2007 September 2007 Version 01.1 01.2 Section -- DC and Switching Characteristics Pinout Information February 2008 01.3 Architecture Initial release. Added JTAG Port Timing Waveforms diagram. Updated sysCLOCK PLL Timing table. Added Thermal Management text section. Added LVCMOS33D to Supported Output Standards table. Clarified: "This Flash can be programmed through either the JTAG or Slave SPI ports of the device. The SRAM configuration space can also be infinitely reconfigured through the JTAG and Master SPI ports." Added External Slave SPI Port to Serial TAG Memory section. Updated Serial TAG Memory diagram. DC and Switching Characteristics Updated Flash Programming Specifications table. Added "8W" specification to Hot Socketing Specifications table. Updated Timing Tables Clarifications for IIH in DC Electrical Characteristics table. Added LVCMOS33D section Updated DOA and DOA (Regs) to EBR Timing diagrams. Removed Master Clock Frequency and Duty Cycle sections from the LatticeXP2 sysCONFIG Port Timing Specifications table. These are listed on the On-chip Oscillator and Configuration Master Clock Characteristics table. Changed CSSPIN to CSSPISN in description of tSCS, tSCSS, and tSCSH parameters. Removed tSOE parameter. Clarified On-chip Oscillator documentation Added Switching Test Conditions Pinout Information Added "True LVDS Pairs Bonding Out per Bank," "DDR Banks Bonding Out per I/O Bank," and "PCI capable I/Os Bonding Out per Bank" to Pin Information Summary in place of previous blank table "PCI and DDR Capabilities of the Device-Package Combinations" Removed pinout listing. This information is available on the LatticeXP2 product web pages Ordering Information April 2008 01.4 DC and Switching Characteristics Added XP2-17 "8W" and all other family OPNs. Updated Absolute Maximum Ratings footnotes. Updated Recommended Operating Conditions Table footnotes. Updated Supply Current (Standby) Table Updated Initialization Supply Current Table Updated Programming and Erase Flash Supply Current Table Updated Register to Register Performance Table Updated LatticeXP2 External Switching Characteristics Table Updated LatticeXP2 Internal Switching Characteristics Table Updated sysCLOCK PLL Timing Table Change Summary (c) 2008 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. www.latticesemi.com 7-1 Lattice Semiconductor Date April 2008 (cont.) Version 01.4 (cont.) Section Revision History LatticeXP2 Family Data Sheet Change Summary DC and Switching Updated Flash Download Time (From On-Chip Flash to SRAM) Table Characteristics (cont.) Updated Flash Program Time Table Updated Flash Erase Time Table Updated FlashBAK (from EBR to Flash) Table Updated Hot Socketing Specifications Table footnotes Pinout Information Updated Signal Descriptions Table Removed Read-Before-Write sysMEM EBR mode. Clarification of the operation of the secondary clock regions. DC and Switching Characteristics Pinout Information Removed Read-Before-Write sysMEM EBR mode. Updated DDR Banks Bonding Out per I/O Bank section of Pin Information Summary Table. Data sheet status changed from preliminary to final. Clarification of the operation of the secondary clock regions. Removed "8W" specification from Hot Socketing Specifications table. Removed "8W" footnote from DC Electrical Characteristics table. Updated Register-to-Register Performance table. Ordering Information Removed "8W" option from Part Number Description. Removed XP2-17 "8W" OPNs. June 2008 01.5 Architecture August 2008 01.6 -- Architecture DC and Switching Characteristics 7-2 |
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